Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity

<table>2D distribution of current flow lines along the cross-section of the proposed device structure in the breakdown state at room temperature.</table>

VLSI Design

fig11

Figure 11

Figure 11: Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity 