Research Article

A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips

Table 1

Definition of parameters.

Parameter definitions

𝑚 Total number of masters

MIDMaster ID
𝑊 0 0 ( 𝑚 , M I D ) A constant component for master M I D when there are 𝑚 masters in the system
𝑆 s l o p e ( 𝑚 , M I D ) A constant slope data for master MID when there are 𝑚 masters in the system
𝐻 𝑞 , s w i t c h Total switching bits from the beat 𝑞 to beat ( 𝑞 + 1 ) within a certain transaction. Here one beat stands for one complete process of transmitting a single data word. The transmission includes both address/control phase and data phase, which are pipelined in AHB protocol and can take multiple cycles.
𝑊 b i t The energy consumption by the logic switching (i.e., excluding wire energy) of a bit
𝑃 i d l e Average value of 𝑃 𝑆 ( 𝑖 )
𝑇 c y c l e Time spent in one clock cycle
𝑛 𝑆 𝑖 Total number of cycles in transaction 𝑖
𝐵 𝑖 , b e a t s Data length of transition 𝑖