Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

Abstract

A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG) is defined as a metric to quantify the most efficient tradeoff. The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability affect the optimal gate sizes in the combined optimization of speed and power.

1. Introduction

 Optimizing a digital circuit for both energy and performance involves a tradeoff, because any implementation of a given algorithm consumes more energy if it is executed faster. The tradeoff between power and speed is influenced by the circuit structure, the logic function, the manufacturing process, and other factors. Traditional design practices tend to overemphasize speed and waste power. In recent years power has become a dominant consideration, causing designers to downsize logic gates in order to reduce power, in exchange for increased delay. However, resizing of gates to save power is often performed in a nonoptimal way, such that for the same energy dissipation, a sizing that results in better performance could be achieved.

In this paper, we explore the energy-performance design space, evaluating the optimal tradeoff between performance and energy by tuning gate sizes in a given circuit. We describe a mathematical method that minimizes the total energy in a combinational CMOS circuit, for a given delay constraint. It is based on an extension of the Logical Effort [1] model to express the dynamic and leakage energy of a path as well as the delay. Starting from the minimum achievable delay, we apply the method for a range of longer delays, in order to find the optimal energy-delay relation for the given circuit. We show that downsizing all gates in a fast circuit by the same factor does not yield an energy-efficient design, and we characterize the differences between gate sizing for high speed and sizing for low power.

In trading off delay for energy, we are interested only in a subset of all the possible downsized circuits2014those implementations that are energy efficient. A design implementation is considered to be energy efficient when it has the highest performance among all possible configurations dissipating the same power [2, 3]. When the optimal implementations are plotted in the energy-delay plane, they form a curve called the energy efficient curve. In Figure 1, each point represents a different hardware implementation. The implementations which belong to the energy efficient family reside on the energy efficient curve.

Figure 1 

Energy efficient curve. Although implementations 0 and 0′ of the given circuit have the same delay (𝐷0), implementation 0 consumes less energy. Similarly, implementations 1 and 1′ consume the same energy, but implementation 1 has a shorter delay (𝐷1), hence is preferable. Points 0 and 1 are on the energy efficient curve. All implementations have the same circuit topology, with different device sizes.

Zyuban and Strenski [3, 4] introduce the hardware intensity metric. Hardware intensity (𝜂) is defined to be the ratio of the relative increase in energy to the corresponding relative gain in performance achievable “locally” through gate resizing and logic manipulation at a fixed power-supply voltage for a power efficient design. Simply put, it is the ratio of % energy per % speed performance tradeoff for an energy-efficient design. Since speed performance is inversely proportional to delay,𝜂=−1/𝐸1/𝐷𝜕𝐸𝜕𝐷,(1) where 𝐷 is delay, 𝐸 is the dissipated energy, and 𝜂 represents the hardware intensity. The hardware intensity is a measure of the “differential” energy-performance tradeoff (the energy gained if the delay is relaxed by a small Δ𝐷 around a given delay and energy point on the energy efficient curve), and is actually the sensitivity of the energy to the delay.

As shown in [3], each point on the energy efficient curve corresponds to a different value of the hardware intensity 𝜂. The hardware intensity decreases along the energy efficient curve towards larger delay values. According to [3], 𝜂 is equivalent to the tradeoff parameter 𝑛 in the commonly used optimization objective function combining energy and delay:𝐹_opt=𝐸⋅𝐷^𝑛,𝑛≥0.(2)

In [5], Brodersen et al. formalize the tradeoff between energy and delay via sensitivities to tuning parameters. The sensitivity of energy to delay due to tuning the size 𝑊_𝑖 of gate 𝑖 is defined as𝜃𝑊_𝑖=−1/𝐸1/𝐷⋅𝜕𝐸/𝜕𝑊_𝑖𝜕𝐷/𝜕𝑊_𝑖,(3) where 𝜃(𝑊_𝑖) is the sensitivity, 𝐷 is the delay, 𝐸 is the energy, 𝜕𝐸/𝜕𝑊_𝑖 is the derivative of energy with respect to size of device 𝑖, and 𝜕𝐷/𝜕𝑊_𝑖 is the derivative of delay with respect to size of device 𝑖. To achieve the most energy-efficient design, the energy reduction potentials of all the tuning variables must be the same. Therefore, for an energy efficient design, (3) is equivalent to (1) for all points on the energy efficient curve.

The focus of this paper is on the conversion to low power of circuits that were optimized only for speed during their initial design process. Optimal downsizing is applied to each gate for each relaxed delay target, such that the whole energy efficient curve is generated for the circuit. Note that the gate sizes are allowed to vary in a continuous manner between a minimum and a maximum size. While the resultant gate sizes would be mapped into a finite cell library in a practical design, the continuous result for some basic circuits provides guidelines and observations about CMOS circuit design for low power.

The rest of this paper is organized as follows: The design scenario is described in Section 2. Usage of logical effort to analyze the delay and energy is described in Section 3. The optimization problem is formalized in Section 4. Typical circuit types are analyzed in Section 5. Section 6 concludes the paper.

2. Power Reduction Design Scenario

Typically, an initial circuit is given, where speed was the only design goal. In order to save energy, the delay constraint is relaxed, and the gates sizes are reduced. For example, consider Figure 1, with the initial circuit implementation 0, which is energy efficient. While relaxing the delay constraint (moving from 𝐷₀ to 𝐷₁), the design gets downsized, which results in circuit implementation 1.

To calculate the energy gain achievable by relaxing the delay by 𝑋 percent, we define a metric we call “Energy Delay Gain” (EDG). The EDG is defined as the ratio of relative decrease in energy to the corresponding relative increase in delay, with respect to the initial design point (𝐷₀, 𝐸₀). 𝐷₀ is the initial delay (not necessarily the minimum achievable delay), and 𝐸₀ is the corresponding initial energy. Note that the EDG defines the total energy-performance tradeoff, as opposed to the differential tradeoff—the hardware intensity. Mathematically, EDG at a given delay 𝐷 with corresponding energy 𝐸 is defined asEDG=𝐸₀−𝐸/𝐸₀𝐷−𝐷₀/𝐷₀.(4)

For example, assuming that the initial design point in Figure 1 is implementation 0, then the EDG of point 1 is𝐸₀−𝐸₁/𝐸₀𝐷₁−𝐷₀/𝐷₀.(5) Figure 2 illustrates the difference between hardware intensity and EDG. It shows the energy efficient curve of a given circuit, where 𝐷₀ is the initial delay, and 𝐸₀ is the corresponding initial energy. The hardware intensity is the ratio between the slope of the tangent to the energy efficient curve at point (𝐷, 𝐸) to the slope of the line connecting the origin to point (𝐷, 𝐸). The EDG is the ratio between the slope of the line connecting points (𝐷₀, 𝐸₀) and (𝐷, 𝐸), to the slope of the line connecting the origin to point (𝐷₀, 𝐸₀). Note that when point (𝐷, 𝐸) is close to (𝐷₀, 𝐸₀), the two definitions converge.

Figure 2 

EDG and hardware intensity. Note that when (𝐷, 𝐸) → (𝐷0, 𝐸0), hardware intensity and EDG converge.

Resizing of the gates to tradeoff performance with active energy is the most practical approach available to the circuit engineer. Continuous gate sizes has been used for optimizing delay under area constraints and vice versa [6]. Other degrees of freedom include logic restructuring, tuning of threshold voltages or supply voltage, and power gating. Changing the threshold voltage affects mainly the leakage energy, and not the dynamic energy dissipation [7, 8], so does power gating [9, 10]. Logic restructuring of the circuit could be an effective method to trade off energy and performance, by reducing the load on high activity nets, and by introducing new nodes that have a lower switching activity [11]. However, changing the circuit topology may increase the time required for the design process to converge. Changing the supply voltage is an effective technique as well [3, 5, 7, 11–14]. However, in most cases, changing the supply voltage for a subcircuit requires major changes in the package and in the system and therefore is not practical. For instance, latest state-of-the art CPUs include only 1-2 power planes [15, 16].

In the following sections, we set up an optimization framework that maximizes the energy saving for any assumed delay constraint in a given combinational CMOS circuit. It determines the appropriate sizing factor for each gate in the circuit. For primary inputs and outputs of the circuit we assume that fixed capacitances. Given activity factor and signal probability are assumed at each node of the circuit. The result of this optimization process is equivalent to finding the energy-efficient curve for the given circuit.

3. Analytical Model

The optimization problem we solve is defined as follows. Given a path in a circuit with initial delay (minimum or arbitrary) 𝐷₀ and the corresponding energy consumption 𝐸₀, find gate sizing that maximizes the EDG for an assumed delay constraint. We use the logical effort method [1] in order to calculate the delay of a path and adapt it to calculate the dynamic and leakage energy dissipation of the circuit.

For a given path (Figure 3), we assume that constant input and output loads and an initial sizing that is given as input capacitance for each gate. For each gate we apply a sizing factor 𝑘. The input capacitance of the resized 𝑖th gate is expressed as the initial input capacitance 𝐶_0𝑖 multiplied by 𝑘_𝑖. The energy-delay design space is explored by tuning the 𝑘’s.

Figure 3 

Example path. Each gate is assigned with logical effort notation, initial input capacitance (𝐶0𝑖) and sizing factor (𝑘𝑖).

The following properties are defined:𝑀_𝑖: number of inputs to gate 𝑖,AF^𝑗_𝑖: activity factor (switching probability) of input 𝑗 in gate 𝑖,AF^𝑖_𝑜:output activity factor of gate 𝑖,𝑔_𝑖:logical effort of gate 𝑖,𝑝_𝑖:parasitic delay of gate 𝑖,𝐶_0𝑖:initial capacitance of gate 𝑖 that achieves initial path delay (corresponds to (𝐷₀, 𝐸₀)),𝐶_off𝑖:off-path constant capacitance driven by gate 𝑖,𝑃_leak𝑖:the average leakage power for gate 𝑖, for a unit input capacitance,𝑘_𝑖:sizing factor for gate 𝑖. The 𝑘's are used in the gate downsizing process. For each gate 𝑖, 𝑘_𝑖⋅𝐶_0𝑖 is the gate size. Although specified, 𝑘₁ is assumed to be 1 (constant driver).

3.1. Energy of a Logic Path

3.1.1. Switching Energy

The switching energy of a static CMOS gate 𝑖 with 𝑀_𝑖 inputs and a single output isSwitchingEnergy=^𝑀𝑖_𝑗=1AF^𝑗_𝑖⋅𝐶_𝑗⋅𝑉²_{𝑗inputenergy}+AF_out𝑖⋅𝐶_out𝑖⋅𝑉²_{out𝑖outputenergy}.(6) Assuming that the voltage amplitude for each net in the design is the same (V_𝑐𝑐), we can define a parameter called dynamic capacitance (𝐶_dyn), which is the switching energy normalized by V_𝑐𝑐. The dynamic capacitance of a gate 𝑖 (𝐶_dyn𝑖) is 𝐶_dyn𝑖=SwitchingEnergyV𝑐𝑐²=^𝑀𝑖_𝑗=1AF^𝑗_𝑖⋅𝐶_𝑗+AF_out𝑖⋅𝐶_out𝑖,(7)

Without loss of generality, we assume that the first input of each gate resides on the investigated path. We assume that the inputs of the gates we deal with are symmetrical (input capacitance on each input pin is equal) and the gates are noncompound (i.e., gates implementing functions like 𝑎⋅𝑏+𝑐 are out of scope). Our method can be easily extended to support these types. Under these assumptions, all input capacitances of a given gate are identical. Therefore, the input 𝐶_dyn of gate 𝑖 (𝐶_dynin𝑖) is𝐶_dynin𝑖=𝐶_0𝑖⋅𝑘^𝑖𝑀𝑖_𝑗=1AF^𝑗_𝑖=𝐶_0𝑖⋅𝑘_𝑖⋅AF_𝑖,(8) where AF_𝑖 is defined to be ∑^𝑀𝑖_𝑗=1AF^𝑗_𝑖—sum of activity factors for input pins of gate 𝑖. Note that unlike calculating the delay of a gate, when calculating the gate energy, all input and output nets of a gate have to be taken into consideration. The 𝐶_dyn of the nets not in the desired path should not be overlooked.

The output capacitance of a gate is defined to be its self loading and is combined mainly of the drain diffusion capacitors connected to the output. The parasitic delay of gate 𝑖 in logical effort method, denoted by 𝑝_𝑖, is proportional to the diffusion capacitance. The logical effort of gate 𝑖, denoted by 𝑔_𝑖, expresses the ratio of the input capacitance of gate 𝑖 to that of an inverter capable of delivering the same current. It is easy to see that the output capacitance of gate 𝑖 can be expressed as𝐶_out𝑖=𝐶_in𝑖𝑔_𝑖𝑝_𝑖.(9)

We can now rewrite (7) using the notation defined previously:𝐶_dyn𝑖=𝐶_0𝑖𝑘_𝑖⋅AF_𝑖+𝐶_0𝑖𝑘_𝑖𝑔_𝑖𝑝_𝑖⋅AF^𝑖_𝑜.(10)

Besides the gates in the path, we have to take into account the 𝐶_dyn of the side loads. Multiplying 𝐶_off𝑖 by AF¹_𝑖 results in the 𝐶_dyn of the off-path load driven by gate 𝑖. We use (10) to calculate 𝐶_dyn of a desired path:𝐶_dyn=AF₁⋅𝐶_{in1input𝐶dyn}+^𝑁_𝑖=2AF_𝑖⋅𝐶_in𝑖+AF^𝑖−1_𝑜⋅𝐶_{out𝑖−1stage𝑖𝐶dyn}+AF^𝑁_𝑜(𝐶_out𝑁+𝐶_load)_{output𝐶dyn}+^𝑁_𝑖=1𝐶_off𝑖⋅AF¹_{𝑖𝐶dynofoffpathload𝑖}.(11)

Substituting input 𝐶_dyn with (8) and 𝐶_out𝑖 with (9), and rearranging the formula, we get𝐶_dyn=^𝑁_𝑖=1𝑘_𝑖AF_𝑖⋅𝐶_0𝑖+AF^𝑖_𝑜⋅𝐶_0𝑖⋅𝑝_𝑖𝑔_𝑖+AF_𝑁+1⋅𝐶_load+^𝑁_𝑖=1𝐶_off𝑖⋅AF¹_𝑖.(12)

By defining𝐶_dyn𝑖≜AF_𝑖⋅𝐶_0𝑖+AF^𝑖_𝑜⋅𝐶_0𝑖⋅𝑝_𝑖𝑔_𝑖,𝐶_dyn-off≜^𝑁_𝑖=1𝐶_off𝑖⋅AF¹_𝑖,(13) we get𝐶_dyn=^𝑁_𝑖=1𝐶_dyn𝑖⋅𝑘_𝑖+AF_𝑁+1⋅𝐶_load+𝐶_dyn-off.(14)

The initial 𝐶_dyn is achieved by setting all 𝑘^_𝑖𝑠 to 1:𝐶⁰_dyn≜𝐶_dyn||_𝑘^_𝑖𝑠=1=^𝑁_𝑖=1𝐶_dyn𝑖+AF_𝑁+1⋅𝐶_load+𝐶_dyn-off.(15)

3.1.2. Leakage Energy

The leakage energy of a static CMOS gate 𝑖 with 𝑀_𝑖 inputs and a single output can be expressed asLeakageEnergyofGate𝑖=𝑇_cycle⋅𝑃_leak𝑖⋅𝐶_0𝑖,(16) where 𝑇_cycle is the cycle time of the circuit, and 𝑃_leak𝑖 is the average leakage power for gate 𝑖, for a unit input capacitance. 𝑃_leak𝑖 is a function of the manufacturing technology, gate topology, and signal probability (SP: the probability for a signal to be in a logical TRUE state at a given cycle) for each input. See [8, 17, 18] for leakage power calculation methods. Under a given workload, 𝑃_leak𝑖 should be precalculated for each gate 𝑖. Since 𝑃_leak𝑖 is sensitive to the signal probability, it needs to be recalculated whenever the workload is modified, to reflect changes in gates’ signal probability.

By dividing the leakage energy by V²_𝑐𝑐, we can express the leakage in terms of capacitance:LeakageCapacitanceofGate𝑖≜𝐶_leak𝑖=1V²_𝑐𝑐𝑇_leak𝑖⋅𝐶_0𝑖⋅𝑃_leak𝑖.(17) And the total 𝐶_leak is equal to:𝐶_leak=1V²_𝑐𝑐𝑇^cycle𝑁_𝑖=1𝑘_𝑖⋅𝐶_0𝑖⋅𝑃_leak𝑖=^𝑁_𝑖=1𝑘_𝑖⋅𝐶_leak𝑖.(18)

The initial 𝐶_leak is achieved by setting all 𝑘^_𝑖𝑠 to 1:𝐶⁰_leak≜𝐶_leak||_𝑘^_𝑖𝑠=1=^𝑁_𝑖=1𝐶_leak𝑖.(19)

By combining (14), (15), (18), and (19) we can express the total capacitance and the initial capacitance of a desired path:𝐶_path=^𝑁_𝑖=1𝑘_𝑖𝐶_dyn𝑖+𝐶_leak𝑖+AF_𝑁+1⋅𝐶_load+𝐶_dyn-off,𝐶⁰_path=^𝑁_𝑖=1𝐶_dyn𝑖+𝐶_leak𝑖+AF_𝑁+1⋅𝐶_load+𝐶_dyn-off.(20)

The energy decrease rate (𝑒_dec) due to downsizing of the gates by a factor of 𝑘 is expressed as𝑒_dec=𝐶⁰_path−𝐶_path𝐶⁰_path=∑^𝑁_𝑖=1𝐶_dyn𝑖+𝐶_leak𝑖1−𝑘_𝑖∑^𝑁_𝑖=1𝐶_dyn𝑖+𝐶_leak𝑖+AF_𝑁+1⋅𝐶_load+𝐶_dyn-off.(21)

In order to estimate the upper bound of 𝑒_dec, we assume an initial design point with minimum delay for 𝐶⁰_path, and set the sizes of the gates in the path to minimum allowed feature size (𝐶_min), to reflect the minimum possible 𝐶_path. By defining𝐶^min_dyn𝑖≜AF_𝑖⋅𝐶_min+AF^𝑖_𝑜⋅𝐶_min⋅𝑝_𝑖𝑔_𝑖,𝐶^min_leak𝑖≜1V²_𝑐𝑐𝑇_cycle⋅𝐶_min⋅𝑃_leak𝑖.(22) We get𝑒_dec⩽𝑒^MAX_dec=∑^𝑁_𝑖=1𝐶_dyn𝑖+𝐶_leak𝑖−∑^𝑁_𝑖=1𝐶^min_dyn𝑖+𝐶^min_leak𝑖∑^𝑁_𝑖=1𝐶_dyn𝑖+𝐶_leak𝑖+AF_𝑁+1⋅𝐶_load+𝐶_dyn-off.(23)

By using (23), the upper bound to the EDG at a given delay increase rate (𝑑_inc)—EDG^MAX_(𝑑inc) can also be calculated, simply by dividing 𝑒^MAX_dec by 𝑑_inc:EDG^MAX_(𝑑inc)=𝑒^MAX_dec𝑑_inc.(24)EDG^MAX_(𝑑inc) can be used by the circuit designer to quickly evaluate the potential for saving power. However, the designer should note that the value of EDG^MAX_(𝑑inc) is a nonreachable upper bound since the minimum sizing leads to a delay increase which is always greater than the one that the designer refers to. If the value of EDG^MAX_(𝑑inc) is not sufficient, other energy reduction techniques should be considered.

3.2. Delay of a Logic Path

When using the logical effort notation, the path delay (𝐷) is expressed as𝐷=^𝑁_𝑖=1𝑔_𝑖ℎ_𝑖+𝑃.(25) The electrical effort of stage 𝑖 (ℎ_𝑖) is calculated as the ratio between capacitance of gate 𝑖+1 and gate 𝑖, plus the ratio of side load capacitance of gate 𝑖 and input capacitance of gate 𝑖. For the sake of simplicity, 𝑘_𝑁+1 and 𝑘₁ are defined to be 1. Using the notation defined earlier, the path delay 𝐷 can be written as:𝐷=^𝑁_𝑖=1𝑔_𝑖⎛⎜⎝𝐶_0𝑖+1𝑘_𝑖+1𝐶_0𝑖𝑘_𝑖+C_off𝑖𝐶_0𝑖𝑘_𝑖⎞⎟⎠+𝑃.(26) By defining 𝐷⁰_𝑖≜𝑔_𝑖𝐶_0𝑖+1𝐶_0𝑖,𝐷¹_𝑖≜𝑔_𝑖𝐶_off𝑖𝐶_0𝑖.(27)Equation (26) becomes𝐷=^𝑁_𝑖=1𝐷⁰_𝑖𝑘_𝑖+1𝑘_𝑖+𝐷¹_𝑖1𝑘_𝑖+𝑃.(28) The initial delay is achieved by setting all 𝑘^_𝑖𝑠 to 1.𝐷₀≜𝐷||_𝑘^_𝑖𝑠=1=^𝑁_𝑖=1𝐷⁰_𝑖+𝐷¹_𝑖+𝑃.(29)

And therefore, the delay increase rate (𝑑_inc) due to downsizing of the gates by a factor of 𝑘_𝑖 is𝑑_inc=𝐷−𝐷₀𝐷₀=∑^𝑁_𝑖=1𝐷⁰_𝑖𝑘_𝑖+1/𝑘_𝑖+𝐷¹_𝑖1/𝑘_𝑖+𝑃−𝐷₀𝐷₀.(30)

4. Optimizing Power and Performance

Given a delay value that is 𝑑_inc percent greater than the initial delay 𝐷₀, we seek the path sizing (𝐶₀₂⋅𝑘₂⋯𝐶_0𝑁⋅𝑘_𝑁) that maximizes the energy reduction rate 𝑒_dec.

From (21), maximizing 𝑒_dec is achieved by minimizing 𝐶_dyn. By ignoring the factors that do not depend on 𝑘_𝑖 and will not affect the optimization process in (20), we define an objective function 𝑓₀:𝑓₀=^𝑁_𝑖=1𝑘_𝑖𝐶_dyn𝑖+𝐶_leak𝑖.(31) Note that 𝑓₀ depends linearly on the dynamic and the leakage capacitances, which apply weights and determine the importance of each 𝑘_𝑖. Equation (31) can also be written as:𝑓₀=^𝑁_𝑖=1𝑘_𝑖𝐶_0𝑖1V²_𝑐𝑐𝑇_cycle𝑃_leak𝑖+AF_𝑖+AF^𝑖_𝑜⋅𝑝_𝑖𝑔_𝑖.(32) Note that when all gates in a path are of the same type, all activity factors are equal, and average leakage power for all gates in the path is equal, both 𝐶_dyn𝑖 and 𝐶_leak𝑖 can be eliminated from (31) without affecting the optimization result. These conditions are satisfied on an inverter chain with input signal probability of 0.5, for instance. In this case, the leakage power of activity factor has no influence on the optimization result.

To get a canonical constraint goal, in which the constraint is less than or equal 1, we rearrange (30) to^𝑁_𝑖=1𝐷⁰_𝑖𝑘_𝑖+1𝑘_𝑖+𝐷¹_𝑖1𝑘_𝑖=𝑑_inc𝐷₀+𝐷₀−𝑃,(33) and define𝐷^0_𝑖≜𝐷⁰_𝑖𝑑_inc𝐷₀+𝐷₀−𝑃,𝐷^1_𝑖≜𝐷¹_𝑖𝑑_inc𝐷₀+𝐷₀−𝑃,(34) to get^𝑁_𝑖=1𝐷^0_𝑖𝑘_𝑖+1𝑘_𝑖+𝐷^1_𝑖1𝑘_𝑖=1.(35)

We now can use (35) to get an optimization constraint𝑓₁=^𝑁_𝑖=1𝐷^0_𝑖𝑘_𝑖+1𝑘_𝑖+𝐷^1_𝑖1𝑘_𝑖⩽1.(36) Combining (32) and (31) results in the following optimization problem:Minimize𝑓₀𝑘₁⋯𝑘_𝑁,subjectto𝑓₁𝑘₁⋯𝑘_𝑁⩽1,where𝑓₀𝑘₁⋯𝑘_𝑁=^𝑁_𝑖=1𝑘_𝑖𝐶_dyn𝑖+𝐶_leak𝑖,𝑓₁𝑘₁⋯𝑘_𝑁=^𝑁_𝑖=1𝐷^0_𝑖𝑘_𝑖+1𝑘_𝑖+𝐷^1_𝑖1𝑘_𝑖.(37) However, 𝑓₁ defined above is nonconvex. We use geometrical programming [19–21] to solve the optimization problem, by changing variables𝑘_𝑖=log𝑘_𝑖⟹𝑘_𝑖=𝑒𝑘_𝑖,𝐶_dyn𝑖=log𝐶_dyn𝑖⟹𝐶_leak𝑖=𝑒𝐶_leak𝑖,𝐶_leak𝑖=log𝐶_leak𝑖⟹𝐶_dyn𝑖=𝑒𝐶_dyn𝑖,𝐷_0𝑖=log𝐷^0_𝑖⟹𝐷^0_𝑖=𝑒𝐷_0𝑖,𝐷_1𝑖=log𝐷^1_𝑖⟹𝐷^1_𝑖=𝑒𝐷_1𝑖.(38)

So the equivalent convex optimization problem (which can be solved using convex optimization tools) is:Minimize𝑓₀𝑘₁⋯𝑘_𝑁,subjectto𝑓₁𝑘₁⋯𝑘_𝑁⩽0,where𝑓₀𝑘₁⋯𝑘_𝑁=log⎛⎜⎝^𝑁_𝑖=1𝑒𝑘_𝑖+𝐶_dyn𝑖+𝑒𝑘_𝑖+𝐶_leak𝑖⎞⎟⎠,𝑓₁𝑘₁⋯𝑘_𝑁=log⎛⎜⎝^𝑁_𝑖=1𝑒𝑘̃‌_𝑖+1−𝑘_𝑖+𝐷_0𝑖+𝑒𝐷_1𝑖−𝑘_𝑖⎞⎟⎠.(39)

The convexity of (39) ensures that a solution to the optimization problem exists, and that the solution is the global optimum point. In order to obtain the EDG curve, the delay increase rate is swept from 0 to the desired value, and for each delay increase value, a different optimization problem is solved by geometrical programming.

This result can be extended to handle circuit delay, instead of a single path delay. All paths must be enumerated, and the optimized delay should reflect the critical path delay. The critical path delay is calculated as the maximum delay of all enumerated paths. However, the MAX operator cannot be handled directly in geometrical programming, since it produces a result which is not necessarily differentiable. Boyd et al. [20] solve the general problem of using the MAX operator in geometrical programming (MAX(𝑓₁(𝑥),𝑓₂(𝑥)…𝑓_𝑁(𝑥))⩽1) by introducing a new variable 𝑡, and 𝑁 inequalities (𝑁 being the number of paths), to obtain𝑡⩽1,𝑓₁(𝑥)⩽𝑡,𝑓₂(𝑥)⩽𝑡,⋯𝑓_𝑁(𝑥)⩽𝑡.(40) This transformation can be used in order to feed the critical path into the optimizer. To calculate the energy-delay tradeoff, the 𝐶_dyn of the entire circuit should be taken into account.

In the following sections, we employ this procedure to characterize the EDG and power reduction in typical logic circuits, and derive design guidelines.

5. Exploring Energy-Delay Tradeoff in Basic Circuits

We run numerical experiments that explore the EDG of some basic circuits. We use GGPLAB [22] as a geometrical programming optimizer, to solve the optimization problem (37) and (39). GGLAB is a free open source library and can be easily installed over Matlab. For each experiment, we provide an EDG curve which is obtained by optimizing the circuit for a wide range of increased delay values. Although the propagation delay and the active energy dissipation are technology independent, the leakage depends on the manufacturing technology and the circuit's cycle time. Throughout this section, the leakage is calculated according to the 32 nm technology node of the ITRS 2007 projection [23], in which 𝐶_leakinv is calculated to be 0.5694, based on clock frequency of 2 GHz and signal probability of 0.5.

5.1. Inverter Chain

Consider a chain consisting of 𝑁 inverters, with output load of 𝐶_out. 𝐶₀₁ is set arbitrarily to a constant value of 1 ff, and therefore the path electrical effort (𝐻) is 𝐶_out (Figure 4). We set initial gate capacitances (𝐶₀₂⋯𝐶_0𝑁) that ensure minimum delay, using the logical effort methodology. The minimum delay was obtained by setting the electrical effort to be the 𝑁th root of the path electrical effort. The leakage calculation takes into account the signal probability of the inverters in the chain.

Figure 4 

Inverter chain—consists of 𝑁 stages, output load 𝐶out, and initial capacitances (𝐶01⋯𝐶0𝑁)

Figure 5(a) shows the EDG for different combinations of path electrical effort (𝐻) and chain length (𝑁) where the leakage energy is negligible. Figure 5(b) shows the same analysis, for negligible dynamic energy. In both cases, the largest potential for energy savings occurs near the point where the design is sized for minimum achievable delay. The potential for energy savings decreases as the delay is being relaxed further. This is consistent with the observation in [5].

(a) Energy delay gain, active dominant circuit

(b)

Figure 5 

Inverter chain—various loads (𝐶out) and chain length (𝑁).

Figure 6 shows the optimal sizing of a fixed input and output load inverter chain with an arbitrary activity factor and signal probability of  0.5, for various delay increase values. For input signal probability of 0.5, all the gates in the inverter chain have the same signal probability. Therefore, the optimization process is indifferent to the average leakage power of each gate—𝑃_leak𝑖 in (17) is constant and can be eliminated from (37).

(a)

(b)

(c)

(d)

(e)

(f)

Figure 6 

Inverter chain—sizing of the stages in an inverter chain. (a) Stage capacitance (chain of 6 inverters), for various delay increase rates (log scale). (b) Stage capacitance (chain of 16 inverters), for various delay increase rates (log scale). (c) Stage sizing factor (chain of 6 inverters): ratio of gate capacitance to minimum delay capacitance, needed to meet the given delay increase rates value. (d) Stage sizing factor (chain of 16 inverters): ratio of gate capacitance to minimum delay capacitance, needed to meet the given delay increase rates value. (e) Stage downsizing value: change in gate capacitance with respect to minimum delay sizes to meet the given delay increase rates value. (f) Stage electrical effort (h), for various delay increase rates.

The optimization process leads to increasing the electrical effort of the last stages and decreasing the electrical effort of the first stages, to meet the timing requirements (Figure 6(f)). The largest energy savings, for a given delay increase value, are achieved by downsizing the largest gates in the chain (Figure 6(e)). The relative downsizing, however, is maximal around the middle of the chain (Figure 6(c)), due to the fact that the first stage and the load are anchored with a fixed size. In order to understand the behavior of the middle stages, a 16-stage inverter stage simulation is plotted in Figure 6(d). As the delay increases, the gates towards the middle of the chain are downsized and form a plateau-like shape. Note that the optimal gate sizes might be limited by the minimum allowed size according to design rules.

Both Figures 6(a) and 6(b) (absolute sizing) and Figure 6(f) illustrate that as we move further from the minimal achievable delay (delay increase = 0, where all electrical efforts are identical), the difference between the electrical efforts of the stages increases. However, uniform downsizing (e.g., increase the delay by downsizing each gate by 5%) is sometimes used in the power reduction process by the circuit designer as an easy and straightforward method to trade off energy for performance. Figure 7 shows the energy efficient curve (optimal sizing) versus energy-delay curve generated by uniform downsizing of an 8-long inverter chain with out/in capacitance ratio of 200. The energy difference between the curves in the figure reaches up to 7%.

Figure 7 

Uniform versus. Optimal downsizing. Linear downsizing of an inverter chain in order to save energy by increasing the delay results in a nonoptimal design—in this case 7% more energy could be saved by tuning the sizing correctly.

Most of the energy in the path is dissipated in the last stages of the chain, where the fanout factors are larger, in order to drive the large fixed output capacitance.

Figure 8 demonstrates the effect of chain length on delay and energy. The external load of the circuit is relatively large—9pF, for which 8-long chain yields an optimal timing. The energy efficient curves for chains of 8, 6, and 4 inverters are plotted in the energy-delay plane. We can see that the number of stages is important when the optimal delay is required. Generally, as we move further from the smallest achievable delay, fewer inverters achieve better energy dissipation for the same delay. However, the difference in energy between the optimal number of inverters and a fixed number of inverters decreases as the delay is relaxed.

Figure 8 

Inverter chain—variable Length: the chain length is varied in order to save a maximal amount of energy for each delay value.

Figure 9 shows good correlation between EDG^MAX_10% see (24), and the actual energy delay gain. The energy saving opportunity increases when the output load is small, and when the number of stages in the path increases.

(a) EDG value of various inverter chains at delay increase rate of 10%

(b) EDGMAX (analytical upper bound to EDG) of various inverter chains at delay increase rate of 10%

Figure 9 

Inverter chain—comparison between energy delay gain and EDGMAX (analytical upper bound to EDG).

5.2. Activity and Signal Probability Effect on Sizing

The more active a gate is, the more energy it consumes. In order to trade off delay and energy better, active gates in the timing critical path can be downsized more than inactive gates in the critical path. For instance, consider the circuit in Figure 10. The path from 𝐴 to out is the timing critical. Input 𝐴 has a fixed activity factor of 0.5, while the activity factor of input 𝐵 is varied. In order to calculate the activity factor and signal probability of internal nodes, the method described in [24] for AF/SP propagation in combinational circuits is used—for a NAND gate with uncorrelated inputs 𝐴 and 𝐵 and output 𝑂, the activity at its output is calculated as:AF_𝑂=AF_𝐴⋅SP_𝐵+AF_𝐵⋅𝑆𝑃_𝐴−12⋅AF_𝐴⋅AF_𝐵.(41) According to (41), the activity factor at the NAND's gate output is AF_nand=0.25+0.5AF_𝐵—the activity factor at the output of the NAND is controlled by the activity factor of input 𝐵, and monotonically rises as AF_𝐵 increases.

Figure 10 

Activity effect on sizing the path from a to end is timing critical, and the activity of input b is varied.

When the delay constrains of the circuit are relaxed, As AF_𝐵 is increased, and with it AF_nand, we expect that the gates that are driven by the NAND gate will get downsized at the expense of the gates driving the NAND gate. Figure 11 shows the sizing factor of each gate for various AF_𝐵 values, for a delay increase rate of 20%. We see that as AF_𝐵 increases, the sizing factor of gates 1 and 2 is increased, while the sizing factor of gates 5 and 6 is decreased.

Figure 11 

Sizing factor to achieve 20% delay increase as AF𝑏 increases, the sizing factor of gates 1 and 2 is increased, while the sizing factor of gates 5 and 6 is decreased.

A similar observation holds for leakage dominant circuits, where the signal probability becomes the affecting parameter instead of the activity factor. 𝑃_leak𝑖 in (16) depends on the signal probability. Therefore, it is expected that the sizing of each gate during the optimization process will be influenced by the signal probability at the gate input. For example, in an inverter, where the 𝑃mos transistor's size is twice the size of the 𝑁mos transistor, the leakage power of a single inverter can be estimated by:InverterLeakagePower=SP⋅𝐶_in⋅23⋅𝑃_leak(𝑃mos)+(1−SP)⋅𝐶_in⋅13⋅𝑃_leak(𝑁mos),(42) where SP is the signal probability in the input of the inverter, 𝐶_in is the input capacitance of the inverter, and 𝑃_leak(𝑁mos,𝑃mos) is the leakage power of 𝑁mos and 𝑃mos transistors respectively, per unit input capacitance. Figure 12 shows the sizes of the gates in a six-stage inverter chain with input capacitance of 1 ff and output load of 600 ff with a small activity factor, when the delay increase rate is varied from 0% to 50%. The optimal sizing at each stage is clearly affected by the signal probability. Up to 50% difference in the sizing of the stages as a function of the signal probability can be observed (see delay increase of 50%, 4th stage).

Figure 12 

Sizing of 6-stages inverter chain as a function of SP the sizing of the stages is sensitive to the signal probability changes, both for small and large delay increase values.

5.3. Comparing Analytical and Simulation-Based Optimization

In order to validate the correctness of the EDG optimization algorithm, the results of Section 5.1 are compared to simulation results. The simulation was performed using a proprietary circuit simulator combined with a proprietary numerical optimization environment, in a 32 nm process. The circuit was first optimized for minimum delay, which was used later as a reference. In order to get the EDG curves, the circuit was optimized by the simulation-based tool for minimum energy, for several delay constraints.

Figure 13 presents the difference between the analytical computation (Section 5.1) and the simulation-based optimization. The error is small, and ranges from a maximum of 7% to a minimum of 0̃‌%. Obtaining the EDG curves using simulation-based optimization is orders of magnitude slower than running the proposed analytical method. Table 1 compares the run time of simulation-based optimization and the run time of the proposed analytical model for few inverter chain circuits. Note that simulation-based optimization run time increases dramatically as the circuit complexity increases.

Table 1 

Comparison of run time-simulation-based and analytical model optimization. The table compares the amount of time taken in order to generate an EDG plot-consists of ten delay increase points.

(a) 𝑁=4;  𝐶out=500 ff

(b) 𝑁=4;  𝐶out=200 ff

(c) 𝑁=8;  𝐶out=500 ff

(d) 𝑁=8;  𝐶out=200 ff

Figure 13 

Simulation optimization of inverter chain with comparison to theoretical computation.

The analytical model was calibrated by computing the parasitics delay of an inverter (𝑝) for the given technology, simply by comparing the output capacitance to the input capacitance of an unloaded inverter (see (9)).

6. Final Remarks and Conclusion

We have presented a design optimization framework that explores the power-performance space. The framework provides fast and accurate answers to the following questions. (1)How much power can be saved by slowing down the circuit by 𝑥 percent? (2)How to determine gate sizes for optimal power under a given delay constraint?

We introduced the energy/delay gain (EDG) as a metric for the amount of energy that can be saved as a function of increased delay. The method was demonstrated on a variety of circuits, exhibiting good correlation with accurate simulation-based optimizations. We have shown that around 25% dynamic energy can be gained when the delay constraint is relaxed by 5% in an optimal way, for circuits in 32 nm technology which were initially designed for maximal operation speed. An upper bound of power savings in a given circuit can be obtained without optimization, in order to quickly assess whether a downsizing effort may be justified for the circuit.

The method described in this work can be used by both circuit designers and EDA tools. Circuit designers can increase their intuition of the energy-delay tradeoff. The following rules of thumb can be derived from the experiments. (i)Minimum Delay Is Power Expensive. By relaxing the delay, significant amount of dynamic energy could be saved. We have shown that under given conditions, for a 2-bit multiplexer up to 40% of dynamic energy could be saved when the delay constraint is relaxed by 10%. (ii)A fixed Uniform Downsizing Factor for all Gates in the circuit would lead to an inefficient design in terms of energy. The optimal downsizing factor is not uniform. (iii)Increase delay by downsizing the “middle” gates. In order to save energy with minimal impact on timing-the gates located in the middle (between he input and the load) are downsized the most. The downsizing factor increases as the delay constraint relaxes. (iv)Increase Delay by Increasing the Electrical Effort towards the load. Minimum delay design requires a constant tapering factor. Typically, a “fanout of 4” is used [1]. Minimum energy design (when neglecting short circuit power) requires high tapering factor, that decreases the number of stages. When performance is compromised to save energy, the tapering factor of the stages must increase towards the external load. The tapering factor increases as the delay constraint is relaxed. Note that this result is applicable only when the external load is larger than the input capacitance. (v)Downsizing of the Gates Reduces Both Dynamic energy and Leakage Energy Dissipation. Both dynamic energy and leakage energy dissipation depend linearly on the size of the gates. By downsizing the gates, both dynamic and leakage energy are reduced. (vi)The Power Optimization Has to Be Performed under a Given Work-load. The activity factor and signal probability influence the optimized circuit's sizing. Different tests may result in different sizing. Using random tests, rather then typical tests to optimize the circuit may lead to sub-optimal design.

Acknowledgments

The authors would like to thank Yoad Yagil for his valuable inputs.