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VLSI Design
Volume 2011 (2011), Article ID 845957, 13 pages
http://dx.doi.org/10.1155/2011/845957
Research Article

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

Department of Electric Engineering, Technion, Israel Institute of Technology, Haifa 32000, Israel

Received 23 September 2010; Accepted 28 January 2011

Academic Editor: Shiyan Hu

Copyright © 2011 Yoni Aizik and Avinoam Kolodny. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Yoni Aizik and Avinoam Kolodny, “Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints,” VLSI Design, vol. 2011, Article ID 845957, 13 pages, 2011. doi:10.1155/2011/845957