Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

<table>Sizing of 6-stages inverter chain as a function of SP the sizing of the stages is sensitive to the signal probability changes, both for small and large delay increase values. </table>

VLSI Design

fig12

Figure 12

Figure 12: Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints 