Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

<table>EDG and hardware intensity. Note that when (<svg height="11.45125" id="M50" style="vertical-align:-0.0pt" version="1.1" viewbox="0 0 13.5925 11.45125" width="13.5925" xmlns="http://www.w3.org/2000/svg">
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VLSI Design

fig2

Figure 2

Figure 2: Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints 