Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

<table>Example path. Each gate is assigned with logical effort notation, initial input capacitance (<svg height="18.272499" id="M61" style="vertical-align:-5.39853pt" version="1.1" viewbox="0 0 20.7225 18.272499" width="20.7225" xmlns="http://www.w3.org/2000/svg">
<g transform="matrix(1.25,0,0,-1.25,0,18.2725)">
<text transform="matrix(1,0,0,-1,0.498,5.881)">
<tspan style="font-size: 12.50px; " x="0" y="0">𝐶</tspan>
</text>
<text transform="matrix(1,0,0,-1,8.888,2.755)">
<tspan style="font-size: 8.75px; " x="0" y="0">0</tspan>
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<text transform="matrix(1,0,0,-1,13.264,0.567)">
<tspan style="font-size: 6.25px; " x="0" y="0">𝑖</tspan>
</text>
</g>
</svg>) and sizing factor (<svg height="15.7125" id="M62" style="vertical-align:-3.2316pt" version="1.1" viewbox="0 0 13.76 15.7125" width="13.76" xmlns="http://www.w3.org/2000/svg">
<g transform="matrix(1.25,0,0,-1.25,0,15.7125)">
<text transform="matrix(1,0,0,-1,0.498,3.72)">
<tspan style="font-size: 12.50px; " x="0" y="0">𝑘</tspan>
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<text transform="matrix(1,0,0,-1,7.275,0.594)">
<tspan style="font-size: 8.75px; " x="0" y="0">𝑖</tspan>
</text>
</g>
</svg>).</table>

VLSI Design

fig3

Figure 3

Figure 3: Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints 