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VLSI Design
/
2011
/
Article
/
Fig 5
/
Research Article
Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints
Figure 5
Inverter chain—various loads (
𝐶
o
u
t
) and chain length (
𝑁
).
(a)
Energy delay gain, active dominant circuit
(b)
