845957.fig.006a
(a)
845957.fig.006b
(b)
845957.fig.006c
(c)
845957.fig.006d
(d)
845957.fig.006e
(e)
845957.fig.006f
(f)
Figure 6: Inverter chain—sizing of the stages in an inverter chain. (a) Stage capacitance (chain of 6 inverters), for various delay increase rates (log scale). (b) Stage capacitance (chain of 16 inverters), for various delay increase rates (log scale). (c) Stage sizing factor (chain of 6 inverters): ratio of gate capacitance to minimum delay capacitance, needed to meet the given delay increase rates value. (d) Stage sizing factor (chain of 16 inverters): ratio of gate capacitance to minimum delay capacitance, needed to meet the given delay increase rates value. (e) Stage downsizing value: change in gate capacitance with respect to minimum delay sizes to meet the given delay increase rates value. (f) Stage electrical effort (h), for various delay increase rates.