Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints : Table 1

Table 1: Comparison of run time-simulation-based and analytical model optimization. The table compares the amount of time taken in order to generate an EDG plot-consists of ten delay increase points.


Circuit	Sim-based optimization	Analytical model optimization

4-long Inverter Chain	240 sec	25 sec
8-long Inverter Chain	360 sec	40 sec
15-long Inverter Chain	1100 sec	70 sec