VLSI Design

Research Article

Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies

Table 3

Performance evaluation using Algorithm 𝑠 𝑡 𝑇 𝑟 𝑒 𝑒 3 for Phase 1 and Algorithm NC for Phase 2 on modified ISPD98 benchmarks (decreased both horizontal and vertical capacity by 1 unit) with polynomial cost function.
Flute Phase 1 Phase 2 Number of XOR gates
o v t o t o v m a x w l e n o v t o t o v m a x w l e n o v t o t o v m a x w l e n
ibm1 3257 14 60209 362 4 78161 184 3 77231 5
ibm2 5678 22 166193 18 1 217673 4 1 217737 12
ibm3 2308 16 145777 1 1 183395 0 0 183391 2
ibm4 4833 15 162844 550 6 193832 440 6 193131 52
ibm5 5 4 410038 0 0 476251 0 0 473265 70
ibm6 5492 27 276012 3 1 334165 1 1 334163 0
ibm7 4665 15 363678 1 1 473743 0 0 473743 2
ibm8 5400 13 403502 3 1 476880 0 0 476864 0
ibm9 8545 14 411524 16 1 496563 9 1 496409 24
ibm10 7103 20 574743 4 1 713569 1 1 713553 18