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VLSI Design
Volume 2012 (2012), Article ID 173079, 18 pages
http://dx.doi.org/10.1155/2012/173079
Research Article

Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

1Department of Electronics Engineering, Institute of Engineering & Technology (IET), Lucknow 226021, India
2Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology (MNNIT), Allahabad 211004, India

Received 28 June 2011; Revised 2 November 2011; Accepted 24 November 2011

Academic Editor: Jose Carlos Monteiro

Copyright © 2012 Subodh Wairya et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Subodh Wairya, Rajendra Kumar Nagaria, and Sudarshan Tiwari, “Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design,” VLSI Design, vol. 2012, Article ID 173079, 18 pages, 2012. doi:10.1155/2012/173079