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VLSI Design
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2012
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Article
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Fig 23
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Research Article
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design
Figure 23
(a) Delay (ps) of XOR-XNOR-based adders. (b) Power (
W) XOR-XNOR-based adders.
(a)
(b)