Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

<table>(a) PDP and EDP of XOR-XNOR based full adder cells with load capacitance (2 fF) at 1.8 V. (b) PDP and EDP of XOR-XNOR based full adder cells with load capacitance (500 fF) at 1.8 V.</table>

VLSI Design

fig25

Figure 25

Figure 25: Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design 