Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

<table>(a) PDP comparison of Majority-function-based full adder cells with capacitance load variation at 1.8 V. (b) PDP comparison of Majority-function-based full adder cells with capacitance load variation at 1 V.</table>

VLSI Design

fig26

Figure 26

Figure 26: Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design 