Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

Table 1

Majority expression of standard logic functions.

Standard Boolean function	Majority expression	Function implementation diagram
𝐹=𝐴	𝑀(𝐴,0,1)
𝐹=𝐴⋅𝐵	𝑀(𝐴,𝐵,0)
𝐹=𝐴⋅𝐵⋅𝐶	𝑀(𝑀(𝐴,𝐵,0),𝐶,0)
𝐹=𝐴⋅𝐵⋅𝐶+𝐴⋅𝐵⋅𝐶	𝑀{𝑀(𝑀(𝐴,0,𝐵),𝐶,0),𝑀(𝑀(𝐴,𝐵,0),𝐶,0),1}
𝐹=𝐴⋅𝐵+𝐴⋅𝐵⋅𝐶	𝑀{𝑀(𝐴,0,𝐵),𝑀(𝑀(𝐴,𝐵,0),𝐶,0),1}
𝐹=𝐴⋅𝐵+𝐵⋅𝐶	𝑀{𝑀(𝐴,0,𝐵),𝑀(𝐵,0,𝐶),1}
𝐹=𝐴⋅𝐵+𝐴⋅𝐵	𝑀{𝑀(𝐴,0,𝐵),𝑀(𝐴,0,𝐵),1}
𝐹=𝐴⋅𝐵+𝐵⋅𝐶	𝑀(𝐵,𝑀(𝐴,1,𝐶),0)
𝐹=𝐴⋅𝐵+𝐵⋅𝐶+𝐴⋅𝐵⋅𝐶	𝑀{𝑀(𝐵,𝑀(𝐴,𝐶,1),0),𝑀(𝐴,𝑀(𝐵,𝐶,0),0),1}
𝐹=𝐴⋅𝐵⋅𝐶+𝐴⋅𝐵⋅𝐶	𝑀{𝑀(𝐴,𝐵,𝐶),𝑀(𝐴,𝐵,𝐶),0}
𝐹=𝐴⋅𝐵⋅𝐶+𝐴⋅𝐵⋅𝐶+𝐴⋅𝐵⋅𝐶	𝑀{𝑀(𝐴,𝐶,0),𝑀(𝐴,𝐵,𝐶),𝑀(𝐴,𝐵,𝐶)}
𝐹=𝐴⋅𝐵+𝐵⋅𝐶+𝐴⋅𝐶	𝑀(𝐴,𝐵,𝐶)
𝐹=𝐴⋅𝐵⋅𝐶+𝐴⋅𝐵⋅𝐶+𝐴⋅𝐵⋅𝐶+𝐴⋅𝐵⋅𝐶	𝑀{𝑀(𝐴,𝐵,𝐶),𝑀(𝐴,𝐵,𝐶),𝐶}