Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

Table 6

Truth table for Majority-function-based full adder.

Inputs			Full adder logic outputs
𝐴	𝐵	𝐶	Carry	Carry	Sum=Maj(𝐴,𝐵,𝐶,Carry,Carry)
0	0	0	0	1	0
0	0	1	0	1	1
0	1	0	0	1	1
0	1	1	1	0	0
1	0	0	0	1	1
1	0	1	1	0	0
1	1	0	1	0	0
1	1	1	1	0	1