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VLSI Design
/
2012
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Article
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Tab 2
/
Research Article
9T Full Adder Design in Subthreshold Region
Table 2
No. of power consuming transitions at different internal nodes.
Figure
1
Figure
2
Proposed
(Figure
3
)
N1
N2
N3
N1
N2
N3
N1
N2
N3
1
4
3
1
3
3
2
2
3