Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped onto Systolic Array

<table>Design space exploration using HLS tool (Tables <a href="../tab7/">7</a> and <a href="../tab8/">8</a>(b)).</table>

VLSI Design

Figure 9: Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped onto Systolic Array 