Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="298396.fig.0011a" src="https://static.hindawi.com/articles/vlsi/volume-2012/298396/figures/298396.fig.0011a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Transformed equivalent CAL </td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="298396.fig.0011b" src="https://static.hindawi.com/articles/vlsi/volume-2012/298396/figures/298396.fig.0011b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Optimized equivalent CAL</td></tr></table></td></tr></table>

<table>Transformed and optimized sum-5 actor.</table>

VLSI Design

fig11

Figure 11

Figure 11: Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs 