Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

Table 4

IDCT2D timing results.

Image size	Xilinx design	Transformed design	Optimized design	VHDL design
Maximum frequency (MHz)	37	37	43	41
Latency (𝜇s)	11.52	82.7	28.4	*
Cadency (MHz)	30	18.49	21.7	71
Processing time (𝜇s/64 Tokens)	1.99	3.4	2.8	0.89
Throughput frequency (MHz)	26.62	0.72	2.43	62.4
Global image processing (FPS)	1064	31	101	2518

*Not mentioned in the literature.