Research Article
Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs
Table 6
IDCT2D area consumption with GAUT.
| Criterion | GAUT design | Optimized design |
| Slice flip flops | 2.080/135.168 (2%) | 1.988/135.168 (2%) | Occupied slices | 2.477/67.584 (3%) | 2.353/67.584 (3%) | 4 input LUTs | 4.243/135.168 (3%) | 4.458/135.168 (3%) | Bonded IOBs | 627/768 (81%) | 49/768 (6%) |
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