Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

<table class="table-group" id="tab7"><tr><td><table class="table"><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr class="thead"><td align="left">Transformation </td><td align="center"> Automatic </td><td align="center"> Manual </td></tr><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr><td align="left">Slice flip flops</td><td align="center">20.452/135.168 (15%)</td><td align="center">12.157/135.168 (8%)</td></tr><tr><td align="left">Occupied slices</td><td align="center">47.576/67.584 (70%)</td><td align="center">43.602/67.584 (67%)</td></tr><tr><td align="left">4 input LUTs</td><td align="center">59.868/135.168 (44%)</td><td align="center">53.417/135.168 (39%)</td></tr><tr><td align="left">Bonded IOBs</td><td align="center"> 41/768 (5%)</td><td align="center"> 41/768 (5%)</td></tr><tr class="table-tr"><td colspan="3"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

VLSI Design

tab7

Table 7

Table 7: Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs 