A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Algorithm 1

Example VHDL process.

process(clock)

begin

 if clock’ event and clock=‘1’ then

  𝑍 <= 𝑋 or 𝑌;

  𝑌<=𝑋 and 𝑌;

 end if;

end process;