VLSI Design / 2012 / Article / Tab 4 / Research Article
A New Length-Based Algebraic Multigrid Clustering Algorithm Table 4 Placement wire length and runtime results comparing one- and two-level AMG-LE clustering with length-driven unclustering to baseline placements without using clustering with three placers on the ISPD05 benchmark suite.
(a) HPWL Circuit Capo Fastplace mPL AMG-LE AMG-LE AMG-LE Baseline (×106 ) 1Lvl (%) 2Lvl (%) Baseline (×106 ) 1Lvl (%) 2Lvl (%) Baseline (×106 ) 1Lvl (%) 2Lvl (%) adaptec1 91 1.5 2.3 87 8.6 8.7 81 −1.1 −1.1 adaptec2 120 14.2 14.5 108 4.0 9.6 97 −0.1 −0.1 adaptec3 254 6.4 5.7 287 15.4 17.2 224 0.6 0.6 adaptec4 — — — 230 8.6 12.7 195 −0.5 −0.5 bigblue1 114 4.0 3.3 107 5.5 7.8 101 0.0 0.0 bigblue2 167 2.7 2.3 181 8.5 12.3 152 −0.3 −0.3 bigblue3 439 3.6 6.4 663 37.0 40.1 492 1.7 1.7 Average — 5.4 5.7 — 12.5 15.5 — 0.0 0.0
(b) Runtime Circuit Capo Fastplace mPL AMG-LE AMG-LE AMG-LE Baseline (× 102 s) 1Lvl (%) 2Lvl (%) Baseline (× 102 s) 1Lvl (%) 2Lvl (%) Baseline (× 102 s) 1Lvl (%) 2Lvl (%) adaptec1 30 −24 −73 5 −79 −109 18 −80 −109 adaptec2 44 2 −49 13 −15 −4 17 −134 −211 adaptec3 81 −32 −107 28 −136 −77 65 −89 −135 adaptec4 — — — 21 −208 −184 45 −258 −199 bigblue1 54 11 −36 6 −158 −141 18 −128 −173 bigblue2 92 −64 −100 23 −299 −278 49 −235 −286 bigblue3 254 −24 −49 139 −45 −78 123 −323 −365 Average — −22 −69 — −134 −125 — −178 −211