VLSI Design / 2012 / Article / Tab 6 / Research Article
A New Length-Based Algebraic Multigrid Clustering Algorithm Table 6 Placement wire length and runtime results comparing one- and two-level AMG-LE clustering with length-driven unclustering without detailed placement to baseline placements without using clustering with three placers on the ISPD05 benchmark suite.
(a) HPWL Circuit Capo Fastplace mPL AMG-LE AMG-LE AMG-LE Baseline (×106 ) 1Lvl (%) 2Lvl (%) Baseline (×106 ) 1Lvl (%) 2Lvl (%) Baseline (×106 ) 1Lvl (%) 2Lvl (%) adaptec1 91 −1.4 −2.7 87 1.8 −1.6 81 5.3 3.1 adaptec2 120 12.6 10.8 108 −0.2 3.6 97 13.7 12.9 adaptec3 254 4.0 2.0 287 12.0 10.8 224 16.4 15.3 adaptec4 — — — 230 4.9 7.4 195 8.0 7.6 bigblue1 114 1.1 0.1 107 −1.7 −2.6 101 −0.4 −2.3 bigblue2 167 1.0 −0.4 181 0.8 2.0 152 3.2 1.6 bigblue3 439 4.3 4.6 663 35.7 37.6 492 30.4 29.1 Average — 3.6 2.4 — 7.6 8.2 — 10.9 9.6
(b) Runtime Circuit Capo Fastplace mPL AMG-LE AMG-LE AMG-LE Baseline (×102 s) 1Lvl (%) 2Lvl (%) Baseline (×102 s) 1Lvl (%) 2Lvl (%) Baseline (×102 s) 1Lvl (%) 2Lvl (%) adaptec1 30 21 17 5 −61 −65 18 32 3 adaptec2 44 34 41 13 −14 10 17 −34 −59 adaptec3 81 19 29 28 −47 −73 65 −22 16 adaptec4 — — — 21 −203 −195 45 −59 −52 bigblue1 54 39 42 6 −95 −74 18 −2 −36 bigblue2 92 −2 −16 23 −128 −114 49 −71 −91 bigblue3 254 11 −4 139 −29 −68 123 −90 −75 Average — 20 18 — −82 −83 — −35 −42