An Efficient Multi-Core SIMD Implementation for H.264/AVC Encoder

<table class="table-group" id="tab2"><tr><td><table class="table"><tr><td class="thead-hr" colspan="5"><hr/></td></tr><tr class="thead"><td align="left"></td><td align="center">Cycles</td><td align="center">Operations</td><td align="center">Load</td><td align="center">Store</td></tr><tr><td class="thead-hr" colspan="5"><hr/></td></tr><tr><td align="left">ANSI C version</td><td align="center">36</td><td align="center">134</td><td align="center">8</td><td align="center">0</td></tr><tr><td align="left">SIMD version</td><td align="center">14</td><td align="center">30</td><td align="center">8</td><td align="center">0</td></tr><tr class="table-tr"><td colspan="5"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

VLSI Design

tab2

Table 2

Table 2: An Efficient Multi-Core SIMD Implementation for H.264/AVC Encoder 