Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing

Table 1

Performance of the MPSoC architectures.

MPSoC	Memory	DRAM interface	Computation capabilities	NoC	Scalability
Homogen.	16 Mbits; L1	1 for each tile	2200 MIPS-ARM + 20 GFLOPS DSP	8 NIs + 8 4-port Routers; 32 bit IP bus at 250 MHz,; 128 bit flit at 500 MHz	Easy for on-chip communication and tiles
Heterogen.	22.5 Mbits; (L1 + L2)	1 shared	250 MIPS-SPARC + 1.25 GOPS + 128 G AD/s	16 NIs + 8 5-port Routers; 32 bit IP bus at 250 MHz,; 128 bit flit at 500 MHz	Easy for on-chip communication, not for tiles