Research Article
Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture
Table 2
Performance comparison for the proposed architecture with existing all-digital designs.
| | Parameter | Proposed architecture | [15] | [16] |
| | Technology | EP2C35F672C6 Altera-FPGA | EP2C35F672C6 Altera-FPGA | EP2C35F672C6 Altera-FPGA | | Area | 330 LEs | 105 LEs | 177 LEs | | Power consumptiona (static, dynamic) | 155.02 mW, 4.38 mW | 155.59 mW, 7.86 mW | 155 mW, 13.31 mW | | Measured RMS jitter | 28.74 ps | 14.82 ps | 15.09 ps | | Measured peak-to-peak jitter | 258.1 ps | 333.26 ps | 526.49 ps | | Maximum output frequency | 440 MHz | 280 MHz | 330 MHz | | Frequency resolution | Fine tunning frequency step = 0.168 MHz | Coarse tunning frequency step = 12.47 MHz | Coarse tunning frequency step = 6.25 MHz | | Multiplication factor | 64 | 8 | 16 | | Portability | Yes | Yes | No | | Phase tracking | Yes | No | No |
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aUsing Altera PowerPlay power analyzer tool.
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