Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

Table 2

Delay, area, and power of various nonredundant 32-bit self-timed RCAs.

Adder realization style	Delay (ns)	Area (μm^2)	Power (μW)
SSSC_HIE_NRL (weak)	8.0	6633 (78)	619.1
DIMS_DSSC_DRE (weak)* [25]	12.8	21833 (1202)	1025.9
Toms_DSSC_DRE (strong) [33]	9.4	10793 (512)	693.1
Toms_DSSC_HE (strong) [33]	9.0	12121 (479)	695.9
Folco et al._DSSC_DRE (weak) [34]	5.9	9417 (426)	740.4
DSSC_DRE (weak)	5.9	14921 (770)	871.9
DSSC_HE (weak)	5.8	10889 (402)	688.4

∗The dual sum, single carry (DSSC) adder realization based on the DIMS method required careful speed-independent logic decomposition to decompose the high fan-in C-gates.