Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper
Figure 5
Use case results. Every configuration is labeled with a 4-tuple, whose elements represent the total number of issue slots, the register file capacity (in 32 bit words), the number of fully featured issue slots, the number of data memories. Execution cycles are reported for the different configurations under emulation. Moreover, the modeled power consumption (expressed in ), area occupation (expressed in ), and total energy consumption (expressed in ) figures are reported.
