Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper
Figure 9
Second use case results. Every horizontal axis captures the number of issue slots inside processors ASIP1 and ASIP2. Execution cycles are reported for the different configurations under emulation. The modeled power consumption (expressed in ) and energy consumption (expressed in ) figures are reported. Values are expressed as offset with respect to a zero-point (lowest value of power and energy consumption).
