Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

Table 2

Power models dependency recap. OPC stands for operation per cycle. Program memory is assumed to have 100% access rate.

	Leakage power	Dynamic power
FU	∝ FU_Port_Size	∝ FU_Port_Size, Access_Rate
IS mux logic	∝ Area	∝ Access_Rate
Register file	∝ Area	∝ RF width, Access_Rate, #ports
Decoder	∝ Area	∝ OPC
Result select network	∝ Area	∝ Access_Rate, OPC
Sequencer	constant	constant
FIFOs	∝ Mem_size	∝ Mem_size, Access_Rate
Program memory	∝ Mem_size	∝ Mem_size
Data memory	∝ Mem_size	∝ Mem_size, Access_Rate