Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms

<table>Evaluation results for real-world images. From left to right: reference image, target image, output of the Sobel detector, output of the Canny detector, disparity map generated by the fixed-support-based architecture, disparity map generated by the ADSW-based architecture.</table>

VLSI Design

fig9

Figure 9

Figure 9: Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms 