Table 7: Comparison of PDS performance for various systems and methods.

WorkImage sizeDisparity RangeFrame rate (fps)PDS (106)AlgorithmPlatform

Yang and Pollefeys [12]512 × 51232N/A289Block-matching (SAD)ATI Radeon 9800 graphics card
Yang et al. [13]384 × 2881612.7722.2Hierarchical belief propagationNVIDIA Geforce 7900 GTX graphics card
Khaleghi et al. [15]160 × 120302011.5Census transform basedBlackFin processor-ADSP-BF561 (600 MHz)
Zinner and Humenberger [16]450 × 3756011.8119.5Census transform basedTexas Instruments TMS320C6414 DSP
Hile and Zheng [19]512 × 4803230235.9Block-matching (SAD)N/A
Miyajima and Maruyama [20]640 × 4808026639Block-matching (SAD)ADM-XRC-II (40 MHz)
Arias-Estrada and Xicotencatl [22]320 × 240167187.2Block-matching (SAD)XCV800HQ240-6 (66 MHz)
Lee et al. [23]640 × 4806430589Block-matching (SAD)XC2V8000 (10 MHz)
Hariyama et al. [24]64 × 646450631327.2Block-matching (SAD)APEX20KE (86 MHz)
Georgoulas and Andreadis [25]800 × 6008055021120Block-matching (SAD)EP4SGX290 (511 MHz)
Ambrosch et al. [26]450 × 37510060010125Block-matching (SAD)EP2S130 (110 MHz)
Díaz et al. [27]1280 × 96029521885Phase basedCustom FPGA, Xilinx Virtex-II (65 MHz)
Darabiha et al. [28]256 × 3602030.355.2LWPC (phase correlation)TM-3A board (Xilinx Virtex-4 2000E FPGA)
Jin et al. [29]640 × 480642304522Census transformVirtex-5 XC4VLX200-10 FPGA (93.1 MHz)
Chang et al. [30]352 × 2886442272.5Minicensus adaptive support weightUMC 90ns Std. Cell
Ambrosch and Kubinger [31]750 × 40060601080SAD-IGMCTAltera Stratix I (133 MHz)
Proposed (System 2)1280 × 102412015023592Edge-based fixed support weight block matching (SAD)ML505 Evaluation Board with Virtex-5 LX110T FPGA (100 MHz)
Proposed (System 4)800 × 6006430922Edge-based adaptive support weight block matching (SAD)ML505 Evaluation Board with Virtex-5 LX110T FPGA (155 MHz)