Research Article
Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms
Table 8
Hardware overheads of the edge-directed fixed-support-based architecture (System 2) (image size = 1280 × 1024, max disparity range = 120, window size = 11 × 11).
| Design unit | Slice LUTs | Slice registers | Block RAMs | DSP48Es | Frequency | (69120) | (69120) | (148) | (64) | (MHz) |
| Edge Detection Unit (EDU) | 2812 (~4%) | 1008 (~3%) | 0 | 0 | 134.6 | ABDIF and BTA | 129 (~0.2%) | 0 | 0 | 0 | N/A | Tree Comparators | 1760 (~2.5%) | 329 (~0.5%) | 0 | 0 | 174.3 | Disparity Computation Unit (DCU) | 47331 (~68%) | 31863 (~46%) | 0 | 0 | 109 | Microblaze system and external Memory CONTROLLER | 7754 (~11%) | 8562 (~12%) | 30 (~20%) | 6 (~9%) | 161.2 |
| Entire system | 66882 (~83.8%) | 41559 (~60%) | 30 (~20%) | 6 (~9%) | 100 |
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