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VLSI Design

Volume 2012 (2012), Article ID 608362, 18 pages

http://dx.doi.org/10.1155/2012/608362

## FastRoute: An Efficient and High-Quality Global Router

^{1}Synopsys Inc., Mountain View, CA 94043, USA^{2}Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA^{3}Cadence Design Systems Inc., San Jose, CA 95134, USA

Received 5 February 2012; Revised 10 April 2012; Accepted 10 April 2012

Academic Editor: Rached Tourki

Copyright © 2012 Min Pan et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

Modern large-scale circuit designs have created great demand for fast and high-quality global routing algorithms to resolve the routing congestion at the global level. Rip-up and reroute scheme has been employed by the majority of academic and industrial global routers today, which iteratively resolve the congestion by recreating the routing path based on current congestion. This method is proved to be the most practical routing framework. However, the traditional iterative maze routing technique converges very slowly and easily gets stuck at local optimal solutions. In this work, we propose a very efficient and high-quality global router—FastRoute. FastRoute integrates several novel techniques: fast congestion-driven via-aware Steiner tree construction, 3-bend routing, virtual capacity adjustment, multisource multi-sink maze routing, and spiral layer assignment. These techniques not only address the routing congestion measured at the edges of global routing grids but also minimize the total wirelength and via usage, which is critical for subsequent detailed routing, yield, and manufacturability. Experimental results show that FastRoute is highly effective and efficient to solve ISPD07 and ISPD08 global routing benchmark suites. The results outperform recently published academic global routers in both routability and runtime. In particular, for ISPD07 and ISPD08 global routing benchmarks, FastRoute generates 12 congestion-free solutions out of 16 benchmarks with a speed significantly faster than other routers.

#### 1. Introduction

As the feature size of modern VLSI design continues to shrink and the on-chip communication becomes extremely complicated, the ascending circuit density poses greater challenges for VLSI routers. Modern designs are liable to congestion problems due to increasing on-chip communication, concentrated routing demands, and limited routing resources. Designs with IP blocks usually create narrow channels which further increase the difficulty of routing. Routability has become a major issue for the large designs. Besides, rapidly growing problem size sets a stringent requirement on the speed of routers.

In order to tackle such a complex issue, the routing problem is usually solved by a two-stage approach: a global routing stage followed by a detailed routing one. Global routing works on abstracted tiles. It allocates the routing demand globally over the circuit area and guides the subsequent detailed routing to finish the track assignment and via creation. Although global routing neglects the routing details such as tracks and design rule check (DRC), it generates interconnect information very close to the final routing implementation and can be used for accurate estimation of interconnect topology, wirelength, congestion, and timing.

In addition to routability issue, the continuous shrinking feature size poses great difficulty on manufacture process. Routing is a key step to consider the design-for-manufacture/yield (DFM/DFY) during the design process. It would determine whether a layout would have high yield or not. Vias, one major source for circuit failure, have larger process variation that impacts the timing/yield of circuits in a less predictable way. Thus via minimization is another important goal for global routing.

Routing is one of the traditional VLSI design automation area along with placement and synthesis. Hu and Sapatnekar [1] gave a detailed survey for global routing algorithms. Recently, the global routing algorithms have been improved significantly with the ISPD2007, and ISPD2008 global routing contests held successfully. In the ISPD2008 invited paper “The Coming of Age of (Academic) Global Routing’’, Moffitt et al. [2] presented the recent progress in the global routing area.

There are two major categories of global routing approaches: concurrent and sequential. Concurrent approach tries to handle multiple nets simultaneously. Albrecht [3] proposed a multicommodity flow approximation algorithm to solve the global routing problem. The flow technique is used to solve a linear programming relaxation of global routing. BoxRouter [4] employed a hybrid approach with the application of ILP to simultaneously handle multiple nets and achieved reasonably good runtime. However, evidence suggests that the integer linear programming based routers run much slower than the sequential routers. Sequential approach generally employs a rip-up and reroute (R&R) framework. It takes an initial routing solution and iteratively improves the solution one net at a time. In each iteration, a net passing through congested area is ripped up and rerouted to avoid the currently congested regions. The sequential approach has been proved to be very effective in practice and considerably faster than concurrent approach.

Most recently developed global routers not only employ this R&R strategy but also proposed different techniques to improve solution quality or speed. Kastner et al. [5] proposed a pattern routing scheme by using L-shaped and Z-shaped patterns to speed up the routing. Hadsell and Madden [6] propose to guide the routing by amplifying the congestion map with a new congestion cost function. In ISPD2007 global routing contest, several routers (BoxRouter 2.0 [7], Archer [8], NTHU-Route [9, 10], NTUgr [11], and FGR [12]) employed a negotiation-based R&R approach which was introduced by PathFinder [13] and successfully applied to FPGA routing. The negotiation-based cost functions are used by maze routing to drive the nets away from consistently congested regions.

In both ISPD2007 and ISPD2008 global routing contests, 3-dimensional benchmarks include the costs on vias for performance evaluation to encourage the global routers to consider the via effect. There are two categories of 3D techniques. The first category tries to solve the 3D problem directly on the 3D routing grids, FGR [12] belongs to this category. The second category employs layer projection to transform the 3D routing problem into a 2D one. After solving the 2D problem, the 2D solutions are mapped to 3D ones by layer assignment. Almost all recent global routers (BoxRouter 2.0 [7], Archer [8], MaizeRouter [14], NTHU-Route [9, 10], NTUgr [11], and default algorithm in FGR [12]) belong to this category. Although theoretically the direct 3D technique should produce better solutions, in practice it is less successful in both solution quality and runtime than 2D routing with layer assignment [15].

In this work, we develop a very efficient and high-quality global router FastRoute to tackle the 3D global routing problem. FastRoute integrates novel techniques introduced in [16–19]. Our key contributions are as follows.(1)A carefully designed framework to perform 3D global routing effectively and efficiently.(2)A congestion-driven, via-aware Steiner tree generation technique to form good starting topologies for multipin nets.(3)A segment shifting technique to direct routing demand away from congested region by moving some tree edges without increasing wirelength.(4)A 3-bend routing technique to quickly explore the routing paths between a source pin and a sink pin with a balance between congestion reduction and control on the number of vias.(5)A multisource multi-sink maze routing technique to reconnect two subtrees in a multipin net without fixing the end points on both subtrees.(6)A virtual capacity technique which is a systematic way to guide the maze routing to avoid congested regions.(7)A new adaptive cost function based on logistic function to direct 3-bend routing and maze routing to find less congested paths.(8)A spiral layer assignment technique to extend a 2D routing solution into its 3D counterpart.

Our first contribution is the FastRoute framework that coordinates the proper functioning of quite a few novel global routing techniques we propose. Although each new technique targets to improve the global routing quality, their cumulative effects could be counteractive. We study the interactions between the various global routing techniques and design the framework to maximize the improvement. The second and third contributions focus on the optimization of tree structure before any actual routing. They can improve the routing quality of nets in congestion free region and effectively reduce the runtime for the actual routing process. The fourth and fifth contributions propose two new routing techniques. While 3-bend routing offers a new degree of balance among congestion reduction, via generation and runtime, multisource and multi-sink maze routing relaxes a major constraint on traditional maze routing and thus greatly improves the quality of global routing. The sixth and seventh contributions are enhancement techniques to further help global router to reduce congestion in a more efficient manner. The last contribution, the spiral layer assignment technique, is a representative of various layer assignment techniques proposed between 2007 and 2010.

This paper is organized as follows. Section 2 introduces the general model in global routing. Section 3 describes the framework while the key techniques and algorithms used in FastRoute are presented in Section 4. The experimental results are provided in Section 5 and we conclude in Section 6.

#### 2. Global Routing Grid Model

During global routing, complex design rules are abstracted away and a design is captured in a grid graph. As illustrated in Figure 1, each layer of the entire routing region is partitioned into rectangular regions called global cells, each of which is represented by one node in the grid graph. The boundary on each metal layer between two global cells is represented by one 3D grid edge in the grid graph on the specific layer. The capacity for a grid edge, that is, , is defined as the maximum number of wires that can cross the grid edge. The usage, that is, , is defined as the actual number of wires crossing the grid edge. The overflow is defined as . In the 3D model, a via is defined as a segment of wire that vertically connects one metal layer to a neighboring layer.

#### 3. FastRoute Framework

FastRoute uses a sequential rip-up and reroute scheme to first solve the 2D version routing problem and later map the 2D solution to 3D by layer assignment. The flow of FastRoute is illustrated in Figure 2.

First, we construct congestion-driven via-aware Steiner topologies for each net followed by segment shifting techniques. After the tree structures are decomposed into 2-pin nets, a pattern routing step using L-shape and Z-shape will initiate the routing solution. We initialize the virtual capacity based on current routing status. The virtual capacity technique is proposed to tackle the congestion problem in a systematic manner to guide the iterative rip-up and reroute stage with an adaptive cost function. During rip-up and reroute, we apply two major techniques: 3-bend routing and multisource multi-sink maze routing to effectively avoid routing congestion and minimize via usage. Finally, after we obtain the 2D solution, we extend it to a full-3D solution by a spiral layer assignment algorithm.

This framework is the most practical one for global routing. Although we see solutions with shorter wirelength generated by full-3D concurrent approach like GRIP [21], that solution quality is achieved by impractically long runtime. The other framework like full 3D approach [12] or concurrent-2D approach [4] do not lead to better solution or shorter runtime. Breaking down 3D global routing problem into 2D routing problem plus layer assignment has achieved the best balance between solution quality and runtime so far. FastRoute uses this framework. But more importantly routing techniques developed do not blindly improve one performance metric at a significant cost of others and they choose a suitable metric to improve in the right place. For congestion, before maze routing, FastRoute does not encourage too much detour because they may create artifical congestion hot spot. L/Z routing and 3-bend routing helps to eliminate easy overflow with short runtime and leave difficult regions for maze routing. On the other hand, via count is properly controlled throughout the routing flow because FastRoute only rips up net in congestion region so routing solution in any stage might be the final solution for one specific net, there might be no opportunity to optimize its routing topology again.

In FastRoute 4, we propose the routing algorithms with one important guideline: for the three performance metrics of wirelength, via count, and routing speed, any technique either improves a single metric without degrading the other two or it improves two metrics with little sacrifice in the one left. Looking at the techniques used in topology generation, routing, and convergence enhancement techniques, everyone of them helps to speed up the routing process and improves wirelength and via. The major routing techniques, like congestion-driven via aware RSMT generation, 3-bend routing, layer assignment techniques, and multisource multi-sink maze routing, improve all three metrics. Other assisting techniques, like the initial congestion estimation and virtual capacity adjustment, use not only little runtime but also provide much accurate information to guide routing techniques to work more efficiently so their aggregate effect is still positive.

#### 4. FastRoute Techniques

##### 4.1. Topology Generation

The first part of FastRoute framework is topology generation. Because FastRoute tries to avoid rip-up and reroute to reduce both wirelength and runtime, the initial tree topology has significant impacts. We find that the topology for each net is the determining factor for the quality of routing solution with regard to routability and the number of vias. So instead of just using rectilinear minimal spanning tree (RMST) or rectilinear Steiner minimal tree (RSMT), FastRoute generates tree topologies that greatly reduce congestion and vias.

###### 4.1.1. Congestion Estimation

Before we can construct Steiner tree to help reduce the routing congestion, we need a congestion map to start with. Since this is the first shot and we are going to update the congestion map in later stages, we are aiming at a very fast but fairly good congestion estimation technique.

First, we generate the Steiner trees for all the nets using FLUTE [22, 23]. FLUTE is a very fast and accurate rectilinear Steiner minimal tree algorithm. It generates optimal RSMT for nets up to degree 9, and is still very accurate for nets up to degree 100, and is much faster than other RSMT algorithms. It is very suitable for our application. Second, after generating the Steiner trees, we break all Steiner trees into 2 pin nets. For every 2 pin net, we assign the demand to the grid edges in the 2D grid graph in the following manner. If the two pins of a net have the same -coordinates or -coordinates, we assign demand 1.0 to each grid edge on the straight line connecting the two pins. If the two pins of a net have different - and -coordinates, we assume two possible L-shape (sometimes called 1-bend) routings for it. For each grid edge on the two L-shape routings, we assign demand 0.5 to it. This gives us the very first congestion map. Finally, in order to make the congestion map more accurate, we perform a fast rip-up and reroute using L-shaped pattern routing. For each 2 pin net, we first remove its routing demand from the congestion map. Then we perform routing based on the current congestion map by taking the L-shape which accumulates least number of overflow. After a full round of L-shaped pattern routing for all 2 pin nets, we obtain a routing solution and its corresponding congestion information. We use it as the congestion map to guide the following congestion-driven via-aware Steiner tree generation.

###### 4.1.2. Congestion-Driven and Via-Aware Steiner Tree Generation

Traditionally, global routing just uses tree structure like RMST or RSMT while RSMT is becoming more popular due to its minimal wirelength to connect a multipin net together. Because congestion and via minimization are not taken into account, simply adopting RSMT as the tree topology becomes insufficient. To address this problem, FastRoute generates routing topologies with consideration of reducing routing congestion and vias. The congestion-driven via-aware Steiner tree topology construction technique has great impact on the routing solution quality. It explores the solution space out of the scope of pattern routing and maze routing.

Routing congestion happens when there is more routing demand than the capacity of grid edges. We find that the congestion in horizontal direction and vertical direction can vary a lot. Due to different routing demand and capacity, it is very common that one direction is highly congested but the other direction is abundant of routing resources. If routing demand can be transferred between two directions, a lot of congestion problems can be easily resolved. However, we notice that neither pattern routing or maze routing is able to shift routing demand in between horizontal and vertical directions once the tree topology is fixed.

In addition, the local routing demand and resource always vary so that local congestion differs a lot. Pattern routing and maze routing have the ability to even out the routing demand, but their effectiveness is limited because both techniques are applied only to 2-pin nets obtained after breaking the routing tree.

One important observation we make is that Steiner tree topologies can provide more flexibility to avoid routing congestion. For a multipin net, there are many different Steiner tree topologies to connect all the pins. Each topology corresponds to some specific routing demand and affects congestion differently. For example, in Figure 3, we show 8 different Steiner tree topologies for a 6-pin net. For each topology, we only show one of the possible embeddings on the routing grids. The number below each column of grid edges is the routing demand over all the grid edges in that column. The number right to each row of grid edges is the routing demand over all the grid edges in that row. Although all these Steiner trees in Figure 3 have the same wirelength, they have very different routing demand distribution, hence result in very different congestion. Therefore, we make use of this flexibility in topology and try to find good topology for each net in terms of congestion metric. For example, for the net shown in Figure 3, if it is congested in horizontal direction, we want to pick topology (a) which has less routing demand in horizontal direction. On the contrary, if it is congested in vertical direction, (h) would be the best choice. In addition to transferring routing demand between two directions, shifting local routing demand in the same direction is also enabled by changing topology. Comparing topology (b) with (e), instead of having more routing demand in the 2nd row (from left) and 2nd column (from top) of grid edges as in (e), topology (b) has more routing demand in the 4th row and 4th column of grid edges. So whether using topology (b) or (e) depends on the congestion of these rows and columns of grid edges.

With this flexibility of topology in mind, our main idea is to construct good Steiner tree for each net according to the congestion map. We encourage using the topology with less routing demand in the congested direction and congested regions. To achieve this goal, we construct Steiner tree topologies in the following way. First, we define the row/column region between two Hanan grid lines for a net as the rectangular region between the two grid lines and the bounding rectangle of the net. As illustrated in Figure 4, the shaded region in (a) is the row region between the Hanan grid lines and , and the distance between and is . Similarly, the shaded region in (b) is the column region between the Hanan grid lines and , and the distance between and is . For each column region or row region between two Hanan grid lines of the original net, we compute their corresponding “average congestion’’ or as where and are the numbers of vertical/horizontal Hanan grid lines within the bounding box, and / are the vertical/horizontal grid edges at /. Then, the distance between the corresponding two Hanan grid lines is scaled according to the “average congestion’’ (the higher the “average congestion’’, the bigger the scaling factor). In other words, we warp the Hanan grid according to the congestion map. Finally, we apply FLUTE to find the RSMT for this warped Hanan grid. In this way, we maintain a balance between wirelength and congestion when constructing the Steiner tree other than just minimizing wirelength.

In addition, we also notice that most global routers merely start to consider via usage only in the R&R stages. Since the majority of nets are in congestion free regions and not involved in R&R, their via usage will stay as the solution before R&R and is not optimized in consideration of via usage. After analysis of net topologies, we find that different tree topologies would have significant impact on the number of vias. As shown in Figure 5, three topologies are generated for a 5-pin net. Assume that horizontal segments are routed on metal layer 1 and vertical segments are routed on metal layer 2, and assume the pins are at metal layer 1. The three topologies will generate 5, 8, and 7 vias, respectively. Here we define two special topologies: horizontal Tree ( Tree) and Vertical Tree ( Tree). tree is defined as a rectilinear tree with only one vertical trunk and all the other trunks connecting pin nodes are horizontal. Similarly, vertical tree is defined as a tree with only one horizontal trunk and all the other trunks coming out of pin nodes are vertical. If each net is assigned onto two adjacent metal layers, which our layer assignment algorithm tries to achieve by keeping segments in one net close to each other, Tree and Tree are two extremes with respect to the number of vias. Other trees, like the RSMT with smaller wirelength shown in Figure 5, have via counts in between. However, it is not always the case that Tree would have less number of vias than Tree. If the resources on metal layer 1 is used up and the net has to go onto layer 2 and 3, it is obvious that Tree is a better choice.

To include via usage into the picture of Steiner tree topology generation, we adjust the net topology by the usage/capacity ratio between horizontal metal layers and vertical ones, as defined in (2) as follows: In the equation, and is the sum of horizontal capacity and usage in the bounding box of each net. Similarly, and is the sum of vertical capacity and usage in the bounding box of each net. We use this factor in concatenation to the congestion driven factor in (1) to extend or shrink the horizontal distances between the pin nodes and use FLUTE to generate adjusted topology for each tree. In this way, we can achieve less via count after pattern routing stage with less than overhead in wirelength and overflow.

###### 4.1.3. Segment Shifting

The Steiner tree topology only specifies the connections between the pins and Steiner nodes in a net. After fixing the topology, there is still flexibility left for congestion optimization. For instance, we can focus on the segment location in the Steiner tree shown as the bold line in Figure 6. We define a segment as a straight concatenation of routing edges that cannot be further extended. With different congestion scenarios, the segment should be shifted to different positions to avoid congested regions.

Our idea is to move some segments out of the congested regions without increasing the Steiner tree wirelength. We observe that if the two endpoints of a horizontal or vertical segment are both Steiner nodes; we can shift this segment freely within a “safe range’’ without increasing the Steiner tree length. For a horizontal/vertical segment between a pair of Steiner nodes and , the “safe range’’ is defined as the shifting range of / coordinates for and so that the Steiner tree length will not be increased when shifting the tree edge -. As illustrated in Figure 7, the “safe range’’ of (a) a horizontal segment or (b) a vertical segment - is . We only consider shifting segment - when both and have degree 3. A Steiner node can only have degree 3 or 4, but degree 4 Steiner node has no flexibility for moving. The way to get this “safe range’’ is as follows. We consider the two neighbors for / which are not /. If - is horizontal, the range for safely moving and is between the -coordinates of two neighboring nodes in the tree ( and in Figure 7(a)). Otherwise, the range for safely moving is between the -coordinates of two neighbor nodes ( and in Figure 7(b)). The “safe range’’ of - is the common part of and , which is in Figure 7. In , the segment - can be shifted freely without increasing the tree wirelength.

If we allow topology change, the “safe range’’ can be extended in some cases. For example, in Figure 8(a), the “safe range’’ for segment - is . Hence, - can at most shift to the same -grid as Steiner node . But we notice that - can be shifted higher than without changing the Steiner tree length. The only problem here is that the topology of the tree needs to be changed. This happens when two Steiner nodes and overlap with each other (as illustrated in Figure 8(b)). In this case, we will exchange the two Steiner nodes and to enable further shifting, which is shown in Figure 8(c). Notice that by exchanging and , we change *topology1* into *topology2*. In Figure 8(c), the new “safe range’’ is . Therefore, now we can explore the full range for -.

After we find the “safe range’’ for a segment -, we need to decide the best position to shift it within the “safe range’’. The criterion for the best position is that the total congestion of all the grid edges on the Steiner tree is minimized. Hence, for every possible position, we evaluate the cost for the tree by adding up the cost on all grid edges used by the tree. Note that we only need to evaluate the demand on the grid edges affected by shifting -, which are all tree edges adjacent to and . Note that some tree edges could be a diagonal tree edge (e.g., tree edge 1- in Figure 7(a)). We do not know which grid edges this tree edge will use. In this case, we consider the two possible L-shape route for it and pick the one resulting in smaller congestion. For these diagonal tree edges, later stages will try to minimize the total demand of grid edges on their routing path.

We apply this segment shifting technique iteratively on all the horizontal/vertical segments in a Steiner tree until the total cost of the tree cannot be improved. After segment shifting, the Steiner tree structures for multipin nets are determined and the nets are broken into a set of 2-pin nets. Later the 3-bend routing and maze routing will focus on these 2-pin nets.

##### 4.2. Routing Techniques

With the congestion-driven and via-aware topology, the next stage of FastRoute is actual routing. We find that there exists significant potential to improve traditional routing techniques in terms of via control and congestion reduction. The most commonly used routing techniques in global routing include L/Z/U pattern routing, monotonic routing, and maze routing, as shown in Figure 9. L/Z/U pattern routing generates limited number of via and has fast speed but cannot effectively reduce congestion. Monotonic routing and traditional maze routing, on the contrary, do better job in solving congestion problem but cannot control via count effectively. Besides, maze routing and U routing allow detour to strengthen the congestion reduction capability. Traditional maze routing is most powerful but suffers from long runtime. So all traditional routing techniques sacrifice one or several quality to improve some others.

To address this problem, we propose 3-bend routing, a fast routing technique with enhanced congestion reduction capability than traditional pattern routing and much less via than maze routing. Even with 3-bend routing, FastRoute has to use maze routing as the last resort for highly congested area. In order to enhance the usefulness of maze routing, we propose a new multisource and multi-sink maze routing technique which greatly improves the flexibility and performance of traditional maze routing.

###### 4.2.1. 3-Bend Routing

A 3-bend route is a 2-pin rectilinear connection that has at most three bends and possible detour. It is much more flexible than L/Z/U route on solving congestion problem. Comparing to monotonic route [17] and maze route, 3-bend route has advantage on having less vias. Figure 10 shows two possible 3-bend routes for a tree edge, and . No L/Z/U routing can avoid the congested area marked as shades. However, the 3-bend route can achieve congestion free routing with least bends possible.

To find the best 3-bend routing path for a 2-pin net, we assume one pin to be the source () and the other one to be the sink (). Without loss of generality, we assume is at the lower-left corner and is at the upper-right corner. We define the possible detouring region as an expanding box for each net. It is calculated depending on the size, location, and congestion of each net. The larger net with more congestion will have a larger expanding box. The pseudocode to compute the best 3-bend path for an - bounding box of size and an expanding box of nodes is given in Algorithm 1.

In the algorithm, and denote the costs for a path going from the point horizontally to the left boundary and vertically to the bottom boundary, respectively. is the cost for using the horizontal grid edge between and while is the cost for using the vertical grid edge between and . To balance wirelength and congestion, we use the same cost function as in maze routing, which will be discussed in Section 4.3.2. Line 2 to Line 9 create two tables that have the cost for a bend-free edge between any points in the expanding box and the left or bottom boundary, from which the cost of a 3-bend path between any two nodes in the expanding box could be easily calculated. A 3-bend path could be concatenated from two L-shaped paths, like using and to form . So we add a break point in the expanding box calculate the cost of the induced L-shaped paths in Lines 13 to 16, from which we can compute the cost of all the possible 3-bend paths and find the best solution. Lines 2 to 9 take time. Lines 10 to 19 also take time. So the complexity of 3-bend routing algorithm for a 2-pin net is , the same as Z routing. It is worth noticing that the algorithm shown in Algorithm 1 may compute some paths with overlapping segments. But they will be automatically excluded because of their higher cost.

The small via count, short runtime, and good congestion solving capability let 3-bend routing become an alternative to maze routing. In the past, only a small percentage of nets would be routed by maze routing but the statement fails to hold as the benchmarks become more complex. We apply 3-bend routing for congested nets before maze routing, which leads to runtime and via count reduction.

###### 4.2.2. Multisource Multi-Sink Maze Routing

Maze routing is used as the last resort to solve congestion in global routing. Originally, maze routing algorithm is designed to find the shortest path connecting two pins in the presence of routing blockages. Later, it has been extended to find a path connecting two pins in such a way that it favors a path that passes through less congested area according to some cost function. It is a very powerful technique to find paths avoiding congestion.

However, traditional maze routing only finds the shortest path between two pins. For multipin nets, a typical way is to break the routing tree into 2-pin nets and route each 2-pin nets by maze routing. We find that this kind of independent edge-by-edge routing scheme for each net fails to generate good routing solutions for the multipin nets. Figure 11 illustrates three different scenarios. The shaded areas denote the congested regions.

*(i) Unnecessary Detour*

Consider the scenario in Figure 11(a). The dashed route “Route1’’ is the maze routing result for tree edge . However, if the path does not need to go from to , “Route2’’ is a better choice in terms of cost.

*(ii) Redundant Routing*

Consider the scenario in Figure 11(b). The dashed route is the maze routing result for tree edge . However, the part on the path is already part of the routing tree, and it is redundant to repeat it.

*(iii) Unintentional Loop*

Consider the scenario in Figure 11(c). The dashed route is the maze routing result for tree edge . A loop is created in the routing tree. It is obvious that this loop is not needed and only the part from to is necessary on the path.

As we can see in these three scenarios, unnecessary wires are used to route the multipin nets. This results in using more routing resources than necessary and causes extra routing congestion. The major defect of this edge-by-edge routing scheme for each net is that the topology information is neglected. When routing a tree edge for multipin nets, global router just needs to rejoin the two disconnected subtree generated by rip-up procedure, no matter where the rejoining path ends.

Beging aware of the problem, we propose a multisource multi-sink maze routing algorithm. The main idea is that the existing routing tree is respected when we route a tree edge for a multipin net. We do not constrain the two endpoints of the routing path to be the original endpoints of the tree edge being routed. As illustrated in Figure 12, suppose we are routing a tree edge in the routing tree for a multipin net . We first remove from and obtain two subtrees and . (Note that and can be just a point.) We treat all the grid points on as sources and all the grid points on as sinks. Then, we apply the multisource multi-sink maze routing to find the best path connecting and to form a tree. In Figure 12, the dotted line from to is the best path to connect and .

Our multisource multi-sink maze routing algorithm is shown in Algorithm 2. In the algorithm, is the distance from to , defined as the total cost of all grid edges passed by the temporary shortest path from to . The algorithm follows the framework of Dijkstra’s algorithm [24]. Lines 1–5 initialize the distance , priority queue , and destination points. Lines 6–17 are the loop similar to Dijkstra’s algorithm. Line 18 just traces back to find the shortest path from to .

Our algorithm finds the least cost routing path from to . Theorem 1 gives the optimality of the algorithm.

Theorem 1. *The path found by multisource multi-sink maze routing algorithm is the least cost routing path from to .*

*Proof. *First of all, note that the cost function is a positive function in our problem. In Line 3, for all the grid points on . Hence, we can assume a super source which replaces all the grid points on and all grid points adjacent to are its neighbor. Similarly, we can assume a super sink which replaces all the grid points on , and all adjacent grid points to . Then the problem is transformed to a single-source, single-sink shortest path problem. The optimality follows the optimality of Dijkstra’s algorithm.

The only thing left is to prove the stopping criterion is correct. Recall that we stop when a destination point on is extracted from . Assume is the first destination point extracted from . For the purpose of contradiction, let be the destination point which is on the shortest path from to . Hence, we have . However, when we extract from , is still in , which means . Because the cost function is positive, will never decrease in later updating. Therefore, we obtain a contradiction that .

Now we analyze the complexity of the algorithm. Assume there are grid points in the search region. Lines 1–5 take time . Each extract-min operation on the priority queue takes time . There are at most iterations for the while loop. For each , there are at most 4 neighbors adjacent to it. The insertion and updating of takes time . The total complexity is therefore .

We apply this multisource multi-sink maze routing algorithm on the tree edges of multipin nets. The runtime of maze routing algorithm is highly related to the size of the search region. In order to speed up the algorithm, we do not search the whole grid graph to find the least cost path. Instead, we use expanding box in the same way as 3-bend routing to significantly reduce the runtime while maintaining good solution quality. In our implementation, the enlarge value is proportional to the size and level of congestion of the original bounding box.

We want to point out one issue for the multisource multi-sink maze routing technique. It can totally change the routing tree structure because the endpoints of new routing path do not need to be the endpoints of the tree edge being routed. For example, in Figure 13, the Steiner tree structure is changed from (a) to (b) because of the new routing of tree edge . Hence, we need to update the Steiner tree structure accordingly after routing each tree edge by multisource multi-sink maze routing.

##### 4.3. Convergence Enhancement Techniques

In addition to new topology and routing techniques, FastRoute integrates several performance enhancement techniques to further improve routing quality and reduce run time. In the 2007 and 2008 ISPD global routing contests, we find that traditional global routing framework may easily get trapped in local minimal of solution space and require significant runtime and control to jump out. In order to solve such problem, we propose two new enhancement techniques to improve the convergence of global routing.

###### 4.3.1. Virtual Capacity Technique

Other recently published academic global routers, including BoxRouter [7], Archer [8], NTHU-R [9, 10], NTUgr [11], and FGR [12], employ negotiation-based maze routing technique, which increments the maze routing cost for consistently congested grid edges. However, such negotiation-based cost adjustment lacks theoretical basis and requires significant tuning before it can work properly.

Instead of negotiation based maze routing technique, we propose virtual capacity, a systematic alternative to handle congestion problem. Virtual capacity tries to use adjusted “virtual capacity’’ instead of original capacity to guide maze routing. Given a global routing solution, consider any congested grid edge . With capacity and capacity , overflow would be . We denote the virtual capacity as . The basic idea of virtual capacity is to reduce the capacity of by units (i.e., set the virtual capacity to ) for the next round of maze routing. Because of the reduction in capacity, grid edge becomes more expensive to use and hence some of its routing demand will hopefully be pushed away. In the ideal situation, exactly units of routing demand will be pushed away in order to bring the congestion back to the level of the previous round, if we measure the overflow using virtual capacity. Thus, the new routing demand will be , that is, the same as the original capacity. In order words, grid edge will not be congested in the second round of global routing. In reality, more or less than units of routing demand might be pushed away because other grid edges cannot absorb or will absorb more than the pushed routing demand. So it is necessary to update the virtual capacities and apply maze routing again to further reduce the overflow.

In Section 4.3.1, we discuss the initialization of virtual capacities. In Section 4.3.1, we describe the updating of virtual capacities during the routing process.

*(a) Virtual Capacity Initialization by Alternative Congestion Estimation (ACE)*

Virtual capacity is initialized by subtracting the overflow of last round of routing from the actual grid edge capacity. But for the first round of routing, we want to predict the overflow in order to use virtual capacity to speed up the convergence. We use adaptive congestion estimation (ACE) technique to predict the overflow. ACE assigns net usage to proper grid edge in a more realistic manner and can estimate overflow much more accurately than traditional probabilistic estimation. We implement the estimation using the following two assumptions. Routing region of each 2-pin net is confined within the bounding box. Fractional usage assignment is allowed. The first assumption suggests that we only consider the grid edges inside the bounding box. The second assumption allows breaking the integer usage into fractional values. The fractional value models the behavior of global router that evenly distributes the routing usage in congested region.

The notation of problem formulation of ACE is shown in Table 1. ACE designs a more realistic usage assignment method to estimate routing demand. In general, it allocates the new routing demand to regions where routing demands are previously low.

Consider the usage assignment of one single 2-pin net, the usage ready to be assigned within the bounding box is 1. Without loss of generality, here we just discuss the assignment for vertical grid edges. The usage assignment algorithm for vertical grid edges is shown in Algorithm 3. Each row is processed independently. Inside one row, grid edges are sorted in a decreasing order according to the value of , which is equal to . is the value of maximum grid edge capacity of row . The algorithm compares the average potential assigned usage with largest current assigned usage. It iteratively excludes the grid edge with largest current assigned usage until an even assignment is possible. The time complexity required for processing single 2-pin net is . Figure 14 illustrates the assignment process.

Due to the sequential manner of usage assignment, the net processing order may significantly affect accuracy. ACE processes smaller span nets with higher priority. The net span represents width of bounding box in vertical grid edge assignment or height of bounding box in horizontal grid edge assignment. Nets with larger spans offer more choices to distribute the net usage. Therefore, we order the nets by net span and perform usage assignment for nets with smaller span first. Algorithm 4 shows the detail of the whole ACE algorithm.

Now we apply ACE to solve the routing example in Figure 15. Consider vertical grid edges along the line . Due to the permutation, the net processing order becomes . After assigning net , current assigned usage becomes . And we will get after assigning net . As it goes on, the final assigned usage will be . So the estimation will not generate any potential congestion, which matches exactly with the optimal routing solution.

After the estimation, virtual capacity will be initialized by (3) as follows: In (3), denotes actual grid edge capacity and is the estimated usage obtained by ACE. The new capacity after subtraction is named virtual capacity, which is in abbreviation.

The time complexity of ACE technique is and following is the detailed analysis. To sort out the order of 2-pin nets, it will take . For each net, the worst case time complexity is , where is the maximum number of horizontal and vertical grids. Hence, in general, the overall worst case time complexity is . But the bounding box of a 2-pin net is generally small. Therefore, on average, ACE accounts for around of total global routing runtime.

*(b) Virtual Capacity Updating*

After the virtual capacity initialization, we use virtual capacity instead of the actual grid edge capacity to guide 3-bend routing and maze routing. As the rip-up and reroute proceeds, FastRoute updates virtual capacity at the end of each routing iteration.

The update method is presented in (4) and (5). Existing overflow is calculated as the difference between grid edge usage and actual grid edge capacity . Virtual capacity will be monotonically decreased for the grid edges that are consistently congested as follows:

It is worth noticing that the overflow calculated in (4) can be negative. When we use negative overflow to adjust virtual capacity, it will go up. Thus, virtual capacity adjustment will automatically reduce the cost for grid edges that were previously congested but currently not. In this way, virtual capacity technique can better utilize grid edges and further enhance the convergence of global router.

###### 4.3.2. Adaptive Maze Cost Function

With virtual capacity, we have a systematic way to model congestion. But we still need a cost function to put it into use when maze router evaluates alternative routes.

We propose a logistic function [25] based adaptive cost function, as shown in (6). In the function, is the coefficient controlling the function curve slope when is below . is adaptively adjusted in different maze routing phases. In the initial phase, is set small to preserve good wirelength. Normally in the first few iterations, many nets need rip-up and reroute. If a large coefficient is applied, those nets would be rerouted with huge detour. While in the final stage of maze routing, the cost function curve is made steep to aggressively drive down the residual overflow. There are two other coefficients in the function. determines the slope when is over . is the cost height which controls the trade off between converging speed and wirelength and would be increased each maze routing iteration as follows:

##### 4.4. Spiral Layer Assignment

There are generally two ways to generate solutions for 3D global routing benchmarks. One is, running routing techniques and layer assignment the concurrently. It overly complicates the problem and is rarely used. The other more popular way first projects the 3D benchmarks from aerial view, finds a solution for the 2D problem and expands the solution to multiple layers. This expansion is called layer assignment, which has significant impact on the number of vias for the final solution. To keep FastRoute fast, we propose a sequential layer assignment algorithm that would assign the 2D solution into routing layers, from lower layers to higher ones. The layer assignment algorithm will not change the aerial view of 2D solution and thus keep the total wirelength. Besides, our algorithm keeps total number of overflow unchanged. Thus, if we can find a congestion-free solution for the 2D global routing problem, we can find a valid solution for the original 3D problem.

In the algorithm, we first sort the nets considering their total wirelength and number of pin nodes. Then we order the segments in each net according to their locations in the net. Finally, we assign layers using dynamic programming, segment by segment, net by net.

Due to the competition of different nets in the assigning sequence and greedy nature of layer assignment, careless early assignment causes later nets switching among the layers and thus generates a large number of unnecessary vias. Smaller nets connecting nearby global cells are considered relatively local and should use lower metal layers. On the contrary, longer nets assigned to upper layers will encounter less switching between layers and will use wider tracks on top layers to achieve better timing. Furthermore, we observe that nets with higher number of pins tend to cause more vias. So we order nets by an increasing order of , where is the total wirelength for a net. Thus, we keep nets with smaller total wirelength and higher pin count on the lower layers.

For each net, we order segments for the following reason. The only layer information for a net is that the pin nodes must go up to at least metal layer 1 to have metal connections. So we order the segments in each net in increasing order of their distance to the pin nodes. Here, the distance is defined as the number of segments the two nodes in a segment have to traverse to reach the nearest pin node. We first assign layers to the segments with 0 distance, that is, segments that have at least one pin node and move onto segments with larger distance. By such an order, we are sure that at least one end of each segment has the information that which layers the pin node ranges between. Thus, we start assigning segments on the periphery of a net and continue inwardly.

As shown in Figure 16, we create a “via grid graph’’ to assign each segment to metal layers. We call each node on the graph a “via node’’. Vertical grid edges represent the possible places to add via while the horizontal grid edges are constructed from the actual 2D path in the “via grid graph’’. We pull straight the original zigzagged 2-pin net to form the horizontal grid edges in the via grid graph and copy the capacity and usage of corresponding grid edge from the original grid graph. We break the segments in a tree into the size of grid edges and assign them to layers one by one. Such breakdown enables us to keep the total number of wirelength and overflow of the 2D solution unchanged. Without loss of generality, we assume sources on the very left column and targets on the right. If we do not know the layer information about the ending node, layers 1 to are all considered to be targets. Here, is the number of metal layers in a benchmark. Otherwise, the target is set to be the spanning range of the ending node.

We associate every via node with a cost, which represents the least number of vias on the paths from the node to any source nodes. Since we do not change the aerial view of a net, a 3D path must and must only use the horizontal segments between two adjacent columns once. Thus, the cost for a node is the same as its left neighbor if there is still routing resource or one plus the cost associated with the upper or lower neighbor nodes, whichever is smaller. The pseudocode to process each segment with wirelength is shown in Algorithm 5.

In the algorithm, line 1 uses time and line 2 takes time. The update of costs from vertical neighbors involves with a series of sorting, comparison, and update, which takes time. However, because of the small number of (typically less than 10 depending on the semiconductor process), we use an implementation. Hence, line 4 to line 8 take . So the complexity of layer assignment for each segment is .

#### 5. Experimental Results

We implemented FastRoute in with Steiner tree package FLUTE and the current version is FastRoute 4.1. All the experiments are performed on a Linux machine with 2.8 GHz Intel processor and 32 GB RAM. We run experiments on ISPD08 global routing contest benchmarks [20]. The benchmark statistics are shown in Table 2. It is worth mentioning that FastRoute 4.1 now adopts a single set of tuning and avoids specific benchmark tuning to demonstrate the effectiveness of global routing framework and techniques presented in this work. On the contrary, all the participants in ISPD08 contest use benchmark specific tuning.

The 2008 set of benchmarks has 8 new benchmarks and 8 benchmarks inherited from 2007. However, when ISPD08 global routing contest considers one unit of via at the same cost of one unit of wirelength, the one held in 2007 charges via at a cost three-times the cost for wirelength. In our experiment, we use the rules set by the 2008 contests which treat wire segments and vias equally.

In Table 3, we compare the performance of FastRoute 4.1 on the ISPD08 global routing contest benchmarks with the top 4 routers besides FastRoute 3.0. Again, FastRoute 4.1 is the fastest router. For the four benchmarks that no one can successfully finish routing without incurring any overflow, FastRoute achieves lowest overflow for two benchmarks. Due to the fact that other groups do not disclose the details about the metal wirelength part and via part of the total wirelength, we only compare the total wirelength. Since no newer data is available for BoxRouter2.0 after the ISPD08 contest, we quote the results for BoxRouter2.0 from ISPD08 global routing contest results. All runtime are scaled to 2.8 GHz.

Comparing to NTHU-R2.0, the 2008 ISPD global routing contest winner, FastRoute achieves and improvement for total wirelength and runtime, respectively, on the 12 routable benchmarks. Comparing to the 2nd place winner, NTUgr, FastRoute 4.1 can finish routing one more benchmark without overflow and can achieve less wirelength in 15x faster speed for 11 benchmarks that the two routers both successfully finished.

Via accounts for to of the total wirelength of FastRoute solutions to the contest benchmarks. Although via has higher resistivity and larger process variation which makes it much more important than before, we still believe that congestion reduction is the most important function for global router. Both of the two recent global routing contests held by ISPD gave highest priority to the overflow of solutions for evaluating the performance of global routers.

Even though most global router that participated in the 2008 ISPD global routing contests have greatly improved over their earlier version in the 2007 contest, we observe that some routers still face two challenges. One is how to handle the congestion left in the final stages. Even though FastRoute 4.1 and NTHU-R2.0 successfully finished routing for newblue1, they both failed newblue4, newblue 7 and bigblue4, with a residue overflow of just less than 150. The huge runtime spent by NTUgr and BoxRouter2.0 on newblue1 showed the inability to solve the few final overflow. Another challenge is the effectiveness for the global routers to balance between reducing the number of overflow and extending wirelength. The conflict incurs due to the fact that one of the most efficient method to reduce congestion is detour, that is, extending wirelength, which could, however, induce congestion in other areas. One important way to effectively control the trade off is through cost function used in maze routing. Although cost functions evolve from step function to logistic function and the variants of logistic functions, the fact that global routers that generates shorter wirelength or longer wirelength can only reduce congestion to a similar level demonstrates that there is considerable potential for the academic global routers to improve in this area.

To demonstrate the effectiveness of the global routing techniques proposed in this paper, we turn off certain techniques to see the performance degradation as shown in Table 4. In the column “No tree adj’’, we turn off the congestion-driven via-aware Steiner tree generation and use unadjusted tree topology directly generated from FLUTE. This configuration of FastRoute leads to more congestion and run time overhead. The “No 3-bend’’ column shows the performance of FastRoute without 3-Bend routing. We observe degradation for all three qualities we focus on, though the degradation is not very significant. However, FastRoute spends more runtime for the four unroutable benchmarks without 3-bend routing, which has explanation in the fact that 3-bend routing is much more efficient than maze routing. The “No VCA’’ column shows results generated by FastRoute without virtual capacity Adjustment. Without convergence assisting techniques, FastRoute only finishes 5 benchmarks without overflow. This configuration also dramatically increase total wirelength and runtime because FastRoute spends much more time running maze routing to try to eliminate overflow. For the last configuration, we turn off net ordering and segment ordering used in the spiral layer assignment and it shows that the two ordering saves of wirelength, which would translate into significantly more percentages of via.

The source code of latest FastRoute 4.1 could be requested for download at http://home.eng.iastate.edu/~cnchu/FastRoute.html. If the reader is interested, one can find all the algorithm and tuning factors inside. The latest FastRoute 4.1 uses a single set of tuning factors. The major factors are bounding box sizes, maze routing iterations, and the factor used in (6) in the cost function. Due to space limit, we only present the philosophy in how to set them, and user can refer to the source code to find the exact value. For bounding box sizes, FastRoute starts at a small value to limit detour at the beginning of routing process. It increases as maze routing iterations proceed but is capped at of the entire grid graph size because a larger bounding box would not help to further eliminate congestion and would increase runtime in vain. FastRoute runs maze routing for at most 100 iterations or as soon as it eliminates all violation. For the coefficient in formula (6), keeps growing to increase the strength to push away nets from congested edges. is set to 10.

#### 6. Conclusion

In this paper, we develop a new global routing tool that focuses on reducing routing congestion and the number of vias. If the runtime bonus used in ISPD08 is considered, FastRoute 4.1 outperforms every single academic global router. In addition, it reduces the via count significantly during global routing.

Our future work will focus on how to control maze routing so that it can make more effective balance between reducing congestion and keeping wirelength small.

#### References

- J. Hu and S. S. Sapatnekar, “A survey on multi-net global routing for integrated circuits,”
*Integration, The VLSI Journal*, vol. 31, no. 1, pp. 1–49, 2001. View at Publisher · View at Google Scholar · View at Scopus - M. D. Moffitt, J. A. Roy, and I. L. Markov, “The coming of age of (academic) global routing,” in
*Proceedings of the ACM International Symposium on Physical Design (ISPD '08)*, pp. 148–155, April 2008. View at Publisher · View at Google Scholar · View at Scopus - C. Albrecht, “Global routing by new approximation algorithms for multicommodity flow,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, vol. 20, no. 5, pp. 622–632, 2001. View at Publisher · View at Google Scholar · View at Scopus - M. Cho and D. Z. Pan, “BoxRouter: a new global router based on box expansion and progressive ILP,” in
*Proceedings of the Design Automation Conference*, pp. 373–378, 2006. - R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, “Pattern routing: use and theory for increasing predictability and avoiding coupling,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, vol. 21, no. 7, pp. 777–790, 2002. View at Publisher · View at Google Scholar · View at Scopus - R. T. Hadsell and P. H. Madden, “Improved global routing through congestion estimation,” in
*Proceedings of the 40th Design Automation Conference*, pp. 28–31, June 2003. View at Scopus - M. Cho, K. Lu, K. Yuan, and D. Z. Pan, “BoxRouter 2.0: architecture and implementation of a hybrid and robust global router,” in
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '07)*, pp. 503–508, November 2007. View at Publisher · View at Google Scholar · View at Scopus - M. M. Ozdal and M. D. F. Wong, “Archer: a history-driven global routing algorithm,” in
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '07)*, pp. 488–495, November 2007. View at Publisher · View at Google Scholar · View at Scopus - J.-R. Gao, P.-C. Wu, and T.-C. Wang, “A new global router for modern designs,” in
*Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '08)*, pp. 232–237, March 2008. View at Publisher · View at Google Scholar · View at Scopus - Y.-J. Chang, Y.-T. Lee, and T.-C. Wang, “NTHU-route 2.0: a fast and stable global router,” in
*Proceedings of the International Conference on Computer-Aided Design (ICCAD '08)*, pp. 338–343, November 2008. View at Publisher · View at Google Scholar · View at Scopus - H. Y. Qien, C. H. Hsu, and Y. W. Chang, “High-performance global routing with fast overflow reduction,” in
*Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '09)*, pp. 582–587, January 2009. View at Publisher · View at Google Scholar · View at Scopus - J. A. Roy and I. L. Markov, “High-performance routing at the nanometer scale,” in
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '07)*, pp. 496–502, November 2007. View at Publisher · View at Google Scholar · View at Scopus - L. McMurchie and C. Ebeling, “PathFinder: a negotiation-based performance-driven router for FPGAs,” in
*Proceedings of the ACM 3rd International Symposium on Field-Programmable Gate Arrays*, pp. 111–117, February 1995. View at Scopus - M. D. Moffitt, “MaizeRouter: engineering an effective Global Router,” in
*Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '08)*, pp. 226–231, March 2008. View at Publisher · View at Google Scholar · View at Scopus - J. A. Roy and I. L. Markov, “High-performance routing at the nanometer scale,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, vol. 27, no. 6, pp. 1066–1077, 2008. View at Publisher · View at Google Scholar · View at Scopus - M. Pan and C. Chu, “FastRoute: a step to integrate global routing into placement,” in
*Proceedings of the International Conference on Computer-Aided Design (ICCAD '06)*, pp. 464–471, November 2006. View at Publisher · View at Google Scholar · View at Scopus - M. Pan and C. Chu, “FastRoute 2.0: a High-quality and efficient global router,” in
*Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '07)*, pp. 250–255, January 2007. View at Publisher · View at Google Scholar · View at Scopus - Z. Yanheng, X. Yue, and C. Chu, “FastRoute3.0: a fast and high quality global router based on virtual capacity,” in
*ASP-DAC International Conference on Computer-Aided Design (ICCAD '08)*, pp. 344–349, November 2008. View at Publisher · View at Google Scholar · View at Scopus - Y. Xu, Y. Zhang, and C. Chu, “FastRoute 4.0: global router with efficient via minimization,” in
*ASP-DAC Asia and South Pacific Design Automation Conference (ASP-DAC '09)*, pp. 576–581, January 2009. View at Publisher · View at Google Scholar · View at Scopus - http://www.ispd.cc/contests/ispd08rc.html.
- T. H. Wu, A. Davoodi, and J. T. Linderoth, “GRIP: scalable 3D global routing using integer programming,” in
*Proceedings of the 46th ACM/IEEE Design Automation Conference (DAC '09)*, pp. 320–325, July 2009. View at Scopus - C. Chu, “FLUTE: fast lookup table based wirelength estimation technique,” in
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (ICCAD '04)*, pp. 696–701, November 2004. View at Scopus - C. Chu and Y.-C. Wong, “FLUTE: fast lookup table based rectilinear steiner minimal tree algorithm for VLSI design,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, vol. 27, no. 1, pp. 70–83, 2008. View at Publisher · View at Google Scholar · View at Scopus - E. W. Dijkstra, “A note on two problems in connexion with graphs,”
*Numerische Mathematik*, vol. 1, no. 1, pp. 269–271, 1959. View at Publisher · View at Google Scholar · View at Scopus - D. von Seggern,
*CRC Standard Curves and Surfaces*, CRC Press, Boca Raton, Fla, USA, 1993.