VLSI Design

Review Article

Flexible LDPC Decoder Architectures

Table 4

Flexible LDPC decoder ASIC implementations. CMOS technology process (Tech), area occupation (A), A_norm (normalized area @ 130 nm), scheduling (sched. TDMP/TPMP), code type (C.T), block length , number of decoding modes supported (DM), flexibility (flex.), dt (design time), rt (run time reconfigurable), decoding iterations (It.), throughput (T.P), clock frequency , PE structure (PE) (serial Se, parallel Pa), number of datapaths (Dp), throughput area ratio (TAR)(Mb/s × It/mm² = T.P × It/A_norm), decoding efficiency (DE) (bits/cycle = T.P × It/f), and flexibility efficiency (FE) (DM × bits/cycle/mm² = DE × DM/A_norm).


Design	Tech. (nm)	mm²	mm²	Sched.	C.T	Bits	DM	Flex.	It.	T.P Mb/s	MHz.	PE	Dp	TAR	DE	FE

		1.337	5.348		QC-WiMAX	576–2304	114		25, 20	48–333			24–96	1245.3	16.7	356.0
[28]	65	3.861	15.444	TDMP	DVB-S2	64800	20	D.T	50, 15	60–708	400	Se	90	687.6	26.6	34.4
		1.023	4.092		QC-WiFi	648–1944	12		25, 20	54–281			27–81	1373.4	14.1	41.4

[29]	65	0.51	2.04	TDMP	WiMedia	1200–1320	8	R.T	5, 3	1120–1220	264	Pa	90	1794.1	13.9	54.5
[30]	90	9.60	20.03	TDMP	DVB-S2	64800	20	R.T	15	181–998	320	Se	360	747.4	46.8	46.7
[31]	90	0.42	0.87	TDMP	QC-WiFi	1944	12	R.T	30	43	294	Pa	324	1482.7	4.4	60.7
[32]	180	3.39	1.768	TDMP	QC-WiMAX	576–2304	114	R.T	10	68	100	Se	24	384.6	6.8	438.5
[33]	130	6.3	6.3	TDMP/TPMP	Block-LDPC	576–2304	114	R.T	15	205	260	Se	24–96	487.5	11.8	213.5
[34]	130	2.46	2.46	Overlapped TDMP	QC-WiMAX	576–2304	114	R.T	15	248–287	150	Se	96	1750.0	28.7	1330.0
[27]	130	3.843	3.843	TDMP/TPMP	QC-WiMAX	576–2304	114	D.T	10,15	83–610	333	Se	24–96	2380.9	18.3	4.8
[35]	90	0.679	1.416	TDMP	QC-WiMAX	576–2304	114	R.T	8–12	200	400	Pa	16	1694.9	4.0	322.0
[36]	90	6.25	13.04	TDMP	QC-WiMAX	576–2304	114	R.T	20	105	150	Se	24–96	161.0	14.0	122.4
[37]	130	8.29	8.29	TDMP	QC-WiMAX	576–2304	19	R.T	2–8	222	83.3	Pa	4–8	214.2	5.3	12.1
[38]	130	4.94	4.94	TPMP	Arbitrary	1536	Arbitrary	R.T	2–8	86	125	Pa	Arbitrary	139.3	1.37	N/A