Review Article
Flexible LDPC Decoder Architectures
Table 5
Flexible LDPC decoders ASIP Implementations. CMOS technology process (Tech), area occupation (A), normalized area (Anorm)@ 130 nm, code type (C.T), flexibility (Flex.) design time (D.T), run time (R.T), maximum throughput (T.P), maximum iterations (It.), number of datapaths (Dp), operating frequency , processing element (PE) (serial Se, parallel Pa), throughput area ratio (TAR)(Mb/s × It/mm2 = t.p × It/Anorm), and decoding efficiency (DE) bits/cycle = t.p × It/.
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