Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Table 2

Truth table for (a) two input AND gate and (b) two input OR gate.

(a)

AND	S0	S1	T0	T1	P0	P1	X
S0	S0	S0	S0	S0	S0	S0	S0
S1	S0	S1	T0	T1	P0	P1	X
T0	S0	T0	T0	P0	P0	T0	X
T1	S0	T1	P0	T1	P0	T1	X
P0	S0	P0	P0	P0	P0	P0	X
P1	S0	P1	T0	T1	P0	P1	X
X	S0	X	X	X	X	X	X

(b)

OR	S0	S1	T0	T1	P0	P1	X
S0	S0	S1	T0	T1	P0	P1	X
S1	S1	S1	S1	S1	S1	S1	S1
T0	T0	S1	T0	P1	T0	P1	X
T1	T1	S1	P1	T1	T1	P1	X
P0	P0	S1	T0	T1	P0	P1	X
P1	P1	S1	P1	P1	P1	P1	X
X	X	S1	X	X	X	X	X