Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Table 6

Comparison with previous works.

Circuit name	Previous work [6]		Previous work [12]		Previous work [13]		Proposed ATPG
	% Fault coverage	Time(s)	% Fault coverage	Time(s)	% Fault coverage	Time(s)	% Fault coverage	Time(s)
c432	35	1019	15	4 hr 42 min	—	—	80	338.05
c880	28	1553	38	2 hr 27 min	54.26	0.1	80	1268.5
c1355	16	3173	36	3 hr 48 min	—	—	33	1865.8
c1908	33	2562	8	10 hr 40 min	24.34	360	15	3762.3
c5315	31	7030	1	24 hr 10 min	49	7.85	57	7151.2
c7552	14	8424	2	28 hr 26 min	52	1326.6	68	9867.03