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VLSI Design
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2012
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Article
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Tab 6
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Research Article
Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder
Table 6
Synthesis results for the interframes mode decision architecture.
FPGA Altera Stratix II
TSMC 0.18
μ
m Standard Cells
Number of ALUTs
Number of DLRs
Max. frequency(MHz)
Area (number of gates)
Max. Frequency(MHz)
5,796
2,859
146.56
85,877
142.40