Research Article

Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder

Table 6

Synthesis results for the interframes mode decision architecture.

FPGA Altera Stratix IITSMC 0.18 μm Standard Cells
Number of ALUTsNumber of DLRsMax. frequency(MHz)Area (number of gates)Max. Frequency(MHz)

5,7962,859146.5685,877142.40