Research Article

Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder

Table 8

Comparison between the proposed intra mode decision architecture and other works.

WorkTechnologyHardware resourcesCycles per MBMax. frequencyHD1080 p fpsMin. frequency (HD1080 p)

Wang [15]UMC 0.18 μm10.302 gates41666 MHz3162.21 MHz
Kao [16]TSMC 0.13 μm11.229 gates67275 MHz
Lin [17]TSMC 0.13 μm94.700 gates*560140 MHz30140 MHz
This workFPGA3.267 ALUTs 2.312 DLRs3698.43 MHz3358.26 MHz
TSMC 0.18 μm28.518 gates36129.1 MHz4398.26 MHz

*Hardware resources corresponding to the complete intra prediction module.