Table 8: Comparison between the proposed intra mode decision architecture and other works.

Work Technology Hardware resources Cycles per MB Max. frequency HD1080 p fps Min. frequency (HD1080 p) Wang [15] UMC 0.18 μm 10.302 gates 416 66 MHz 31 62.21 MHz Kao [16] TSMC 0.13 μm 11.229 gates 672 75 MHz — — Lin [17] TSMC 0.13 μm 94.700 gates* 560 140 MHz 30 140 MHz This work FPGA 3.267 ALUTs 2.312 DLRs 36 98.43 MHz 335 8.26 MHz TSMC 0.18 μm 28.518 gates 36 129.1 MHz 439 8.26 MHz

*Hardware resources corresponding to the complete intra prediction module.