Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors

<table>Area/performance tradeoffs for the data-identification-based communication partitioning shown at (a), and the same partitioned network when realized using multistage switches shown at (b).</table>

VLSI Design

fig14

Figure 14

Figure 14: Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors 