Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map

Table 2

Latencies and data widths of AM.

Module	Data widths	Latency (clock cycles)
Inputs	𝑎,𝑏 (64 bit)	—
Multiplier	64 bit	8
Adder	64 bit	8
Output	Result (64 bit)	—