A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

Abstract

We propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of many logic blocks interconnected by a generic three-stage three-sided rearrangeable polygonal switching network (PSN). The main component of this PSN consists of a polygonal switch block interconnected by crossbars. In comparing our PSN with a three-stage three-sided clique-based (Xilinx 4000-like FPGAs) (Palczewski; 1992) switching network of the same size and with the same number of switches, we find that the three-stage three-sided clique-based switching network is not rearrangeable. Also, the effects of the rearrangeable structure and the number of terminals on the network switch-efficiency are explored and a proper set of parameters is determined to minimize the number of switches. Moreover, we explore the effect of the PSN structure and granularity of cluster logic blocks on the switch efficiency of PFPGA. Experiments on benchmark circuits show that switches and speed performance are significantly improved. Based on experiment results, we can determine the parameters of PFPGA for the VLSI implementation.

1. Introduction

Field Programmable Gate Arrays (FPGA’s) [1, 2] are now widely used for the implementation of digital circuits and many commercial products. A typical symmetric FPGA, consisting of an array of logic blocks (Ls) that can be connected by general routing resources, is shown in Figure 1. The routing resources comprise segments of wires and two kinds of blocks, switch blocks (SBs), and connection blocks (CBs). Both the switch and connection blocks contain many programmable switches. The input and output pins of a logic block are connected to its surrounding connection blocks, which in turn are connected to the switch blocks. An arbitrary digital circuit is divided into several parts such that each part is realized by a logic block; then these logic blocks are interconnected by routing resources in an FPGA.

Figure 1 

A typical symmetric FPGA model and its routing resources.

Since the programmable switches usually have high resistance and capacitance and occupy a large area, the number of programmable switches used in an FPGA affects its speed performance, die size, and routability. The time delay along an interconnection path is significant and often exceeds the delay of logic blocks. The routing area of FPGA typically takes from 70 to 90% of the total area [3]. Intuitively, increasing the number of programmable switches of routing network in an FPGA deliver good routability. However, routing network with fewer programmable switches can reduce the impedance of interconnecting paths, and the overall interconnecting speed of the FPGA can thus be improved.

We propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of many logic blocks interconnect by a three-stage three-sided rearrangeable polygonal switching network. Figure 2 shows a model of polygonal FPGA, which consists of many clusters of logic block and 𝐼/𝑂 pins interconnected by a three-stage three-sided polygonal switching network. The polygonal switching network is a three-stage three-sided switching network for connecting inputs of logic-block (𝑃_𝐼), outputs of logic-block (𝑃_𝑂), and 𝐼/𝑂 pins (𝑃_𝑃) to interconnect each other. A 3-sided switch network means that we have three disjoint sets (𝑃_𝑃, 𝑃_𝐼, and 𝑃_𝑂) of terminals to be connected. Furthermore, in the 3-stage switching network, the longest connection of terminals is the length passing through 3 switches. Through the arrangement of switches (or interconnects) in various combinations, a terminal in one set can be connected to a terminal in any other set. Assuming that all connections are point-to-point connections, the enumeration of any pair of the above three sets of terminals to be connected is called an assignment, where a terminal of the three sets can appear in at most one pair. An assignment for a network is realizable if there exist in the network disjoint paths connecting every pair of terminals given in the assignment. A 3-sided switching network is rearrangeable [4–8] if any given assignment is realizable. Since a rearrangeable switching network has better capability to accomplish a given assignment, we focus on the design of a rearrangeable 3-sided switching network for the interconnection of terminals in a PFPGA.

Figure 2 

A polygonal FPGA model and its routing resources: CB𝑃 = {CB1, CB2}, CB𝑂 = {CB3, CB4}, CB𝐼 = {CB5, CB6, CB7, CB8}, 𝑠𝑝=2, 𝑠𝑜=2, and 𝑠𝑖=4.

Studies on multistage switching networks are fruitful. Yen and Feng [5] proposed a class of 2log₂𝑁-stage two-sided networks, which are equivalent to Benes networks. All networks in this class are nonblocking and rearrangeable. The one-stage one-sided rearrangeable switching networks have been discussed by Mitchell and Wild [6]; then, the reduction of crosspoints in the one-stage one-sided crosspoint switching network has been investigated by Varma and Chalasani [7]. Gordon and Srikanthan [8] studied another multistage one-sided switching network with many 2×2 switch elements. Chang et al. and Shyu et al. [9–11] proposed universal switch blocks that can improve the routability in a Xilinx 4000-like (clique-based) FPGAs routing network. Fan et al. [12] designed and proved a class of optimum Polygonal Switch Block PSB(𝑚,𝑆) for all even 𝑚 and 𝑆≥2. Yen et al. [13] proposed rearrangeable switch network that can improve the routability for a binary fat tree. However, most of the studies are concerned with either the two-sided rearrangeable switching networks or the one-stage one-sided rearrangeable switching networks. As well as, in terms of the number of switches, the one-sided or two-sided switching network is not efficient for interconnecting the three disjoint sets of terminals. Thus, this paper presents a generic three-stage three-sided rearrangeable switching network for Polygonal Field Programmable Gate Array by using Polygonal Switching Blocks (PSBs) [14–16] and crossbars. We investigate how to use PSBs to construct a rearrangeable 3-sided Polygonal switching network (PSN) and how to minimize the number of switches repaired. We also compare our PSN with a three-stage 3-sided clique-based (Xilinx 4000-like FPGAs) polygonal switching network of the same size and with the same number of switches and derive that the three-stage 3-sided clique-based polygonal switching network is not rearrangeable.

The next section gives a description on our polygonal FPGA model, 3-sided polygonal switching network, and some notations and definitions. In Section 3, we prove that our 3-sided switching polygonal network is rearrangeable, while Section 4 shows how we minimize the number of switches in a rearrangeable PSN. In Section 5, we propose a polygonal field programmable gate array that consists of many logic blocks interconnected by a PSN. Conclusions are reported in Section 6.

2. Polygonal Field Programmable Gate Array

Figure 2 shows a model of polygonal FPGA, which consists of many clusters of logic block and 𝐼/𝑂 pins interconnected by a generic three-sided Polygonal Switching Network. In this study, we investigate the logic block based on a cluster of 4-input look-up tables (LUTs). The reason is that most research has focused on LUT-based logic blocks, and Rose et al. [17] showed that a 4-input LUT is the most area-efficient LUT. The three-sided polygonal switching network consists of 𝑆 connection blocks (CBs) and an 𝑆-sided polygonal switch block (PSB). Each connection block is connected to one of the 𝑆 sides of the polygonal switch block. All the above blocks contain many programmable switches. The polygonal switching network is a three-stage three-sided switching network for connecting inputs of logic-block, outputs of logic-block, and 𝐼/𝑂 pins to interconnect each other. First, the input and output pins of cluster-based logic blocks and 𝐼/𝑂 pins are connected to the related connection blocks (CBs), which are then interconnected by a polygonal switch block. That is, the first and third stages consist of 𝑆 CBs, and the second stage is a PSB with 𝑆 sides. In this PFPGA, any two terminals of the three groups in a PFPGA can be connected with fewer than three switches. Thus, the speed performance of a PFPGA can be improved.

Since routing area in an FPGA is typically more than the active area, so we investigate how to use PSBs to construct a rearrangeable 3-sided Polygonal Switching Network (PSN) and how to minimize the number of switches repaired in the following section. We also compare our PSN with a three-stage 3-sided clique-based polygonal switching network of the same size and with the same number of switches and derive that the three-stage 3-sided clique-based polygonal switching network is not rearrangeable.

2.1. Three-Sided Polygonal Switching Network

The proposed generic three-stage 3-sided polygonal switching network (PSN) can be used to interconnect terminals in pairs of the three disjoint sets (𝑃_𝑃, 𝑃_𝑂, and 𝑃_𝐼). This PSN consists of 𝑆 crossbars (CBs) interconnected by a 𝑆-side polygonal switch block (PSB). Figure 3(a) shows an example of PSN, where the first and third stages are composed of 8 CBs; and the second (internal) stage is a PSB with 8 sides.

(a)

(b)

Figure 3 

(a) A 3-sided switching network PSN(𝑛,𝑚,𝑠𝑝,𝑠𝑜,𝑠𝑖) with 𝑛=2, 𝑚=2, 𝑠𝑝=2, 𝑠𝑜=2, and 𝑠𝑖=4. (b) The connecting instance in a CB𝑖(𝑛,𝑚).

As shown in Figure 3(b), each crossbar in a PSN, denoted as CB_𝑖(𝑛,𝑚) for 𝑖=1,2,…,𝑆, is an 𝑛×𝑚 block architecture, where 𝑛 is the number of external terminals connected to one of the three sets and 𝑚 is the number of internal terminals connected to one side of PSB, 𝑚∈even [12]. We classify connection blocks CB𝑠 under three groups: CB_𝐼, CB_𝑂, and CB_𝑃, which are used to connect the inputs and outputs of logic-blocks and 𝐼/𝑂 pins, respectively. Denote that CB_𝑃={CB₁, CB₂, …, CB_𝑠𝑝}, CB_𝑂={CB_𝑠𝑝+1, CB_𝑠𝑝+2, …, CB_{𝑠𝑝+𝑠𝑜}}, CB_𝐼={CB_{𝑠𝑝+𝑠𝑜+1}, CB_{𝑠𝑝+𝑠𝑜+2}, …, CB_{𝑠𝑝+𝑠𝑜+𝑠𝑖}}, where 𝑠_𝑝, 𝑠_𝑜, and 𝑠_𝑖 are the number of CBs in the CB_𝑃, CB_𝑂, and CB_𝐼, respectively. As shown in Figure 2, the 𝐼/𝑂 pins are connected to CB_𝑃 = {CB₁,CB₂}, and inputs and outputs of logic-blocks are connected to CB_𝐼={CB₅, CB₆, CB₇, CB₈} and CB_𝑂={CB₃, CB₄}, respectively. Therefore, a three-sided polygonal switching network should provide 𝑁_𝐼=𝑠_𝑖×𝑛, 𝑁_𝑂=𝑠_𝑜×𝑛, and 𝑁_𝑃=𝑠_𝑝×𝑛 external terminals to connect the inputs and outputs of logic-block and 𝐼/𝑂 pins, respectively.

We label these external and internal terminals on a CB_𝑖(𝑛,𝑚) as 𝑃_𝑖={𝑝_𝑖,1, 𝑝_𝑖,2, …, 𝑝_𝑖,𝑛} and 𝑇_𝑖={𝑡_𝑖,1, 𝑡_𝑖,2, …, 𝑡_𝑖,𝑚}, respectively. We represent the external terminals of a CB_𝑖(𝑛,𝑚)𝑃_𝑃=𝑃₁∪𝑃₂∪⋯∪𝑃_𝑠𝑝 (𝐼/𝑂 terminals), 𝑃_𝑂=𝑃_𝑠𝑝+1∪𝑃_𝑠𝑝+2∪⋯∪𝑃_{𝑠𝑝+𝑠𝑜} (output terminals), and 𝑃_𝐼=𝑃_{𝑠𝑝+𝑠𝑜+1}∪𝑃_{𝑠𝑝+𝑠𝑜+2}∪⋯∪𝑃_{𝑠𝑝+𝑠𝑜+𝑠𝑖} (input terminals). Similarly, the internal terminals are denoted as 𝑇_𝑃=𝑇₁∪𝑇₂∪⋯∪𝑇_𝑠𝑝, 𝑇_𝑂=𝑇_𝑠𝑝+1∪𝑇_𝑠𝑝+2∪⋯∪𝑇_{𝑠𝑝+𝑠𝑜}, and 𝑇_𝐼=𝑇_{𝑠𝑝+𝑠𝑜+1}∪𝑇_{𝑠𝑝+𝑠𝑜+2}∪…∪𝑇_{𝑠𝑝+𝑠𝑜+𝑠𝑖}. In total, we have two sets of terminals: the external terminal set 𝒫=𝑃_𝑃∪𝑃_𝑂∪𝑃_𝐼 and the internal terminal set 𝒯=𝑇_𝑃∪𝑇_𝑂∪𝑇_𝐼 in a PSN. Furthermore, the set of 𝑃_𝑃, 𝑃_𝑂, and 𝑃_𝐼 have 𝑁_𝑃=𝑠_𝑝×𝑛, 𝑁_𝑂=𝑠_𝑜×𝑛, and 𝑁_𝐼=𝑠_𝑖×𝑛 external terminals, respectively. Similarly, the set of 𝑇_𝑃, 𝑇_𝑂, and 𝑇_𝐼 have 𝑀_𝑃=𝑠_𝑝×𝑚, 𝑀_𝑂=𝑠_𝑜×𝑚, and 𝑀_𝐼=𝑠_𝑖×𝑚 internal terminals on 𝑆CB(𝑛,𝑚) crossbars. For example, Figure 3(a) shows a 3-sided switching network PSN with 𝑃_𝑃=𝑃₁∪𝑃₂, 𝑃_𝑂=𝑃₃∪𝑃₄, and 𝑃_𝐼=𝑃₅∪𝑃₆∪𝑃₇∪𝑃₈, where 𝑃_𝑖={𝑝_𝑖,1,𝑝_𝑖,2}, 𝑖=1,2,…,8; and with 𝑇_𝑃=𝑇₁∪𝑇₂, 𝑇_𝑂=𝑇₃∪𝑇₄, and 𝑇_𝐼=𝑇₅∪𝑇₆∪𝑇₇∪𝑇₈, where 𝑇_𝑖={𝑡_𝑖,1,𝑡_𝑖,2}, 𝑖=1,2,…,8. Any pair of external terminals from two sets of 𝑃_𝑃, 𝑃_𝑂, and 𝑃_𝐼 can be connected to each other by using a 3-sided switching network PSN, but no pair external terminals from the same set can be interconnected.

Through the 𝑛×𝑚 programmable and electrically noninteracting switches in a crossbar CB_𝑖(𝑛,𝑚), every external terminal in 𝑃_𝑖 can be connected to a free internal terminal in 𝑇_𝑖 without any blocking. For example, if switch SW(𝑝_𝑖,𝑗,𝑡_𝑖,ℎ) is programmed to be “ON”, then connection (𝑝_𝑖,𝑗,𝑡_𝑖,ℎ) between an external terminal 𝑝_𝑖,𝑗 and an internal terminal 𝑡_𝑖,ℎ is established, where 1≤𝑖≤𝑆, 1≤𝑗≤𝑛, and 1≤ℎ≤𝑚. Figure 3(b) shows a routing example, where 𝑝_𝑖,1 is connected to 𝑡_𝑖,2 by programming SW(𝑝_𝑖,1,𝑡_𝑖,2), and this routing solution is illustrated by thick lines. In such a way, an external terminal can be connected to an internal terminal by programming one switch in a CB_𝑖(𝑛,𝑚).

The polygonal switch block in a PSN, denoted as a PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), is an 𝑆-side switch block with 𝑚 internal terminals on each side of the block, as shown in Figures 4(a) and 5(a). Label the terminals on the 𝑖th side of a PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) as 𝑇_𝑖={𝑡_𝑖,1,𝑡_𝑖,2,…,𝑡_𝑖,𝑚} for 1≤𝑖≤𝑆. Remember that internal terminals 𝒯=𝑇_𝑃∪𝑇_𝑂∪𝑇_𝐼, where 𝑇_𝑃=𝑇₁∪𝑇₂∪⋯∪𝑇_𝑠𝑝, 𝑇_𝑂=𝑇_𝑠𝑝+1∪𝑇_𝑠𝑝+2∪⋯∪𝑇_{𝑠𝑝+𝑠𝑜}, and 𝑇_𝐼=𝑇_{𝑠𝑝+𝑠𝑜+1}∪𝑇_{𝑠𝑝+𝑠𝑜+2}∪⋯∪𝑇_{𝑠𝑝+𝑠𝑜+𝑠𝑖}. If a switch SW(𝑡_𝑖,𝑗,𝑡_𝑘,𝑙) exists in PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) and is programmed to be “ON”, then a connection between terminals 𝑡_𝑖,𝑗 and 𝑡_𝑘,𝑙 is established, where 𝑡_𝑖,𝑗 and 𝑡_𝑘,𝑙 belong to two different sets of 𝑇_𝑃, 𝑇_𝑂, and 𝑇_𝐼. To form a 3-sided switching network PSN we need 𝑆CB(𝑛,𝑚) crossbars connected to a polygonal switch block PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). Thus, a 3-sided switching network can be completely characterized by five parameters: 𝑛,𝑚,𝑠_𝑝,𝑠_𝑜, and 𝑠_𝑖, and denoted as PSN(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), for 𝑛≥2, 𝑚∈even, 𝑠_𝑝≥1, 𝑠_𝑜≥1, 𝑠_𝑖≥1, and 𝑆=𝑠_𝑝+𝑠_𝑜+𝑠_𝑖. For example, Figure 3(a) shows a PSN with 𝑛=2, 𝑚=2, 𝑠_𝑝=2, 𝑠_𝑜=2, and 𝑠_𝑖=4.

Figure 4 

(a) A polygonal switch block PSB𝐶(𝑚,𝑠𝑝,𝑠𝑜,𝑠𝑖) with 𝑚=2, 𝑠𝑝=2, 𝑠𝑜=2, and 𝑠𝑖=4; and (b) Its correspondence to two PSB𝐶(1,2,2,4).

Figure 5 

A polygonal switch block PSBSU(𝑚,𝑠𝑝,𝑠𝑜,𝑠𝑖) with 𝑚=4, 𝑠𝑝=2, 𝑠𝑜=2, and 𝑠𝑖=4. (b) Its correspondence to two PSBSU(2,2,2,4).

As shown in Figures 4(a) and 5(a), we will study the 3-sided switching network with two different topologies of polygonal switch blocks in this paper, denoted as PSB_𝐶(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) and PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), respectively. Algorithm 1 constructs a clique-based polygonal switch block PSB_𝐶(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). As shown in Figure 4, a PSB_𝐶(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is equivalent to 𝑚 isolated PSB_𝐶(1,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). In Figure 6 we show a 3-sided switching network, PSN_𝐶(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) constructed with a PSB_𝐶(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). Algorithm 2 constructs the polygonal switch block PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). As shown in Figure 5, a PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is equivalent to 𝑚/2 isolated PSB_SU(2,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), 𝑚∈even. A 3-sided switching network PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) consisting of 𝑆CB(𝑛,𝑚) crossbars connected to a PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is shown in Figure 7. Table 1 lists some symbols of 3-sided switching network specified in this paper.

Table 1 

Summary of symbols.

Algorithm: Clique-based PSB𝐶(𝑚,𝑠𝑝,𝑠𝑜,𝑠𝑖,𝒯,SW). Input: 𝑆=𝑠𝑖+𝑠𝑜+𝑠𝑝—number of sides of the polygonal switch block; 𝑚—number of terminals on each side of the polygonal switch block, 𝑚∈even. Output: (𝒯,SW); 𝒯 =𝑇𝑃∪𝑇𝑂∪𝑇𝐼: set of terminals; SW: set of switches. (1)  Let internal terminals 𝑇𝑃=𝑇1∪𝑇2∪⋯∪𝑇𝑠𝑝,    𝑇𝑂=𝑇𝑠+1∪𝑇𝑠+2∪⋯∪𝑇𝑠𝑝+𝑠𝑜 and    𝑇𝐼=𝑇2𝑠+1∪𝑇2𝑠+2∪⋯∪𝑇𝑠𝑝+𝑠𝑜+𝑠𝑖,   where 𝑇𝑖={𝑡𝑖,1,𝑡𝑖,2,…,𝑡𝑖,𝑚} for 1≤𝑖≤𝑆. (2)   SW←∅; (3)   for  𝑖=1  to  𝑠𝑖  do (4)    for  𝑘=𝑠𝑖+1  to  𝑆  do (5)       for  𝑗=1  to  𝑚  do (6)         SW←SW∪{(𝑡𝑖,𝑗,𝑡𝑘,𝑗)}; (7)  for  𝑖=𝑠𝑖+1  to  𝑠𝑖+𝑠𝑜  do (8)   for  𝑘=𝑠𝑖+𝑠𝑜+1  to  𝑆  do (9)       for  𝑗=1  to  𝑚  do (10)         SW←SW∪{(𝑡𝑖,𝑗,𝑡𝑘,𝑗)}; (11)   Return  (𝒯,SW)

Algorithm 1 

Algorithm for constructing an 𝑆-sided clique-based switch block of size 𝑚.

Algorithm: Semi-universal PSBSU(𝑚,𝑠𝑝,𝑠𝑜,𝑠𝑖,𝒯,SW). Input: 𝑆=𝑠𝑖+𝑠𝑜+𝑠𝑝—number of sides of the polygonal switch block; 𝑚—number of terminals on each side of the polygonal switch block, 𝑚∈even. Output: (𝒯,SW); 𝒯=𝑇𝑃∪𝑇𝑂∪𝑇𝐼: set of terminals; SW: set of switches. (1)   Let internal terminals 𝑇𝑃=𝑇1∪𝑇2∪⋯∪𝑇𝑠𝑝,    𝑇𝑂=𝑇𝑠𝑝+1∪𝑇𝑠𝑝+2∪⋯∪𝑇𝑠𝑝+𝑠𝑜 and   𝑇𝐼=𝑇𝑠𝑝+𝑠𝑜+1∪𝑇𝑠𝑝+𝑠𝑜+2∪⋯∪𝑇𝑠𝑝+𝑠𝑜+𝑠𝑖,   where 𝑇𝑖={𝑡𝑖,1,𝑡𝑖,2,…,𝑡𝑖,𝑚} for 1≤𝑖≤𝑆. (2)   SW←∅; (3)   for  𝑖=1  to  𝑠𝑝  do (4)     for  𝑘=𝑠𝑝+1  to  𝑆  do (5)       for  𝑗=1  to  𝑚  do (6)         SW←SW∪{(𝑡𝑖,𝑗,𝑡𝑘,𝑚−𝑗+1)}; (7)   for  𝑖=𝑠𝑝+1  to  𝑠𝑝+𝑠𝑜  do (8)     for  𝑘=𝑠𝑝+𝑠𝑜+1  to  𝑠𝑝+𝑠𝑜+𝑠𝑖  do (9)       for  𝑗=1  to  𝑚  do (10)        SW←SW∪{(𝑡𝑖,𝑗,𝑡𝑘,𝑚−𝑗+1)}; (11)   Return  (𝒯,SW)

Algorithm 2 

Algorithm for constructing an 𝑆-sided semi-universal switch block of size 𝑚.

Figure 6 

A PSN𝐶(𝑛,𝑚,𝑠𝑝,𝑠𝑜,𝑠𝑖) with 𝑛=2, 𝑚=2, 𝑠𝑝=2, 𝑠𝑜=2, and 𝑠𝑖=4.

Figure 7 

A PSNSU(𝑛,𝑚,𝑠𝑝,𝑠𝑜,𝑠𝑖) with 𝑛=2, 𝑚=2, 𝑠𝑝=2, 𝑠𝑜=2, and 𝑠𝑖=4.

Note that we do not allow any two external terminals from the same set of 𝑃_𝑃, 𝑃_𝑂, and 𝑃_𝐼 to be interconnected in a PSN(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). Similarly, we do not allow any two internal terminals from the same set of 𝑇_𝑃, 𝑇_𝑂, and 𝑇_𝐼 to be interconnected in a PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). For example, Figures 4(a) and 5(a) show that PSB_𝐶(2,2,2,4) and PSB_SU(4,2,2,4) do not have any switches between the two sets of 𝑇₁ and 𝑇₂ from the same 𝑇_𝑃 for the interconnection. That is, in either a PSN_𝐶(2,2,2,2,4) (Figure 6) or a PSN_SU(2,2,2,2,4) (Figure 7) no interconnections of external terminals from the same sets of 𝑃₁ and 𝑃₂ through PSB_𝐶(2,2,2,4) or PSB_SU(2,2,2,4) are allowed. In a PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) or PSB_𝐶(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), since a terminal from a side in one set of 𝑇_𝑃, 𝑇_𝑂, and 𝑇_𝐼 should be connected to any other terminal from the sides in the remaining two sets through switches, a polygonal switch block needs at least 𝑚(𝑠_𝑝𝑠_𝑜+𝑠_𝑝𝑠_𝑖+𝑠_𝑜𝑠_𝑖) switches. Assume that both 3-sided switching networks PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) and PSN_𝐶(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) have the same size and the same number of switches. We will show that the three-stage 3-sided switching network PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) with 𝑚≥𝑛 is rearrangeable and 𝑚 is even [12], but the PSN_𝐶(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) with 𝑚=𝑛 is not rearrangeable.

In a PSN(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), the connection pair (𝑝_𝑖,𝑗,𝑝_𝑘,𝑙) is a point-to-point connection, where 𝑝_𝑖,𝑗 and 𝑝_𝑘,𝑙 belong to different sets of 𝑃_𝑃, 𝑃_𝑂, and 𝑃_𝐼. An assignment AS={(𝑝_𝑖,𝑗,𝑝_𝑘,𝑙)} represents a set of connection pairs to be connected; thus each external terminal appears in at most one pair. A PSN(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) switching network is rearrangeable if any assignment AS is realizable (routable).

Note that a connection pair (𝑝_𝑖,𝑗,𝑝_𝑘,𝑙) belonging to AS is to be connected by passing through blocks CB−PSB−CB. Given an AS on a PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), each pair of connection is accomplished using terminals from two different sides of 𝑇_𝑃, 𝑇_𝑂, and 𝑇_𝐼; we can thus classify these connections passing through a PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) into (𝑠_𝑝𝑠_𝑜+𝑠_𝑝𝑠_𝑜+𝑠_𝑜𝑠_𝑖) types of connections. Figure 8 shows the twenty possible types of connections in an eight-side switch block PSB(𝑚,2,2,4). A routing requirement vector (RRV)𝑟⃗ [9–11] for a PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is a (𝑠_𝑝𝑠_𝑜+𝑠_𝑝𝑠_𝑜+𝑠_𝑜𝑠_𝑖)-tuple (𝑟_1,𝑠𝑝+1, 𝑟_1,𝑠𝑝+2, …, 𝑟_{1,𝑠𝑝+𝑠𝑜+𝑠𝑖},𝑟_2,𝑠𝑝+1, …, 𝑟_{2,𝑠𝑝+𝑠𝑜+𝑠𝑖}, …, 𝑟_{𝑠𝑝,𝑠𝑝+1}, …, 𝑟_{𝑠𝑝,𝑠𝑝+𝑠𝑜+𝑠𝑖}, …, 𝑟_{𝑠𝑝+𝑠𝑜,𝑠𝑝+𝑠𝑜+𝑠𝑖}), where 𝑟_𝑖,𝑘 represents the number of type-(𝑖,𝑘) connections between 𝑇_𝑖 and 𝑇_𝑘 required to be connected through a PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖); 0≤𝑟_𝑖,𝑘≤𝑚 for 1≤𝑖<𝑘≤𝑆. In other words, 𝑟_𝑖,𝑘 is the number of connections {(𝑝_𝑖,𝑗,𝑝_𝑘,𝑙)} in AS to be connected through the two sides 𝑇_𝑖 and 𝑇_𝑘 on a PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), 1≤𝑗,𝑙≤𝑚, where 𝑇_𝑖 and 𝑇_𝑘 belong to any two different sets of 𝑇_𝑃, 𝑇_𝑂, and 𝑇_𝐼. An RRV 𝑟⃗ is said to be realizable (routable) on a PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) if there exist disjoint paths for 𝑟⃗ on a PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). Figure 8 shows an RRV 𝑟⃗ = (𝑟_1,3, 𝑟_1,4, 𝑟_1,5, 𝑟_1,6, 𝑟_1,7, 𝑟_1,8, 𝑟_2,3, 𝑟_2,4, 𝑟_2,5, 𝑟_2,6, 𝑟_2,7, 𝑟_2,8, 𝑟_3,5, 𝑟_3,6, 𝑟_3,7, 𝑟_3,8, 𝑟_4,5, 𝑟_4,6, 𝑟_4,7, 𝑟_4,8) for PSB with eight sides.

Figure 8 

Twenty possible types of connections in an eight-side switch block.

For example, Figure 9(a) shows a routing instance with three nets corresponding to the RRV 𝑟⃗ = (1_1,3, 0, 0, 0, 1_1,7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1_3,7, 0, 0, 0, 0, 0), and we try to route this RRV using the two different polygonal switch blocks PSB_𝐶(2,2,2,4) and PSB_SU(2,2,2,4) from Figures 4(a) and 5(b), respectively. As shown in Figures 9(b) and 9(c), however, there is always one net that cannot be routed on a PSB_𝐶(2,2,2,4). Thus, this RRV (1_1,3, 0, 0, 0, 1_1,7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1_3,7, 0, 0, 0, 0, 0) is not routable on a PSB_𝐶(2,2,2,4). Instances of the same RRV 𝑟⃗ routable on a PSB_SU(2,2,2,4) are shown in Figures 10(a) and 10(b), where the routing solutions are illustrated by thick lines.

(a)

(b)

(c)

Figure 9 

Examples of routing on a PSB𝐶(2,2,2,4). (a) An RRV instance (11,3, 0, 0, 0, 11,7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13,7, 0, 0, 0, 0, 0). (b), (c) The RRV is not routable on a PSB𝐶(2,2,2,4).

(a)

(b)

Figure 10 

(a), (b) An RRV (11,3, 0, 0, 0, 11,7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13,7, 0, 0, 0, 0, 0) routable on a PSBSU(2,2,2,4).

Each connection pair (𝑝_𝑖,𝑗,𝑝_𝑘,𝑙)∈AS is required to be connected by passing through CB_𝑖−PSB−CB_𝑘 in a PSN(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). Given an AS={(𝑝_𝑖,𝑗,𝑝_𝑘,𝑙)}, we want to obtain an RRV 𝑟⃗=(𝑟_1,𝑠𝑝+1,𝑟_1,𝑠𝑝+2,…,𝑟_{1,𝑠𝑝+𝑠𝑜+𝑠𝑖},𝑟_2,𝑠𝑝+1,…,𝑟_{2,𝑠𝑝+𝑠𝑜+𝑠𝑖},…,𝑟_{𝑠𝑝,𝑠𝑝+1},  …,𝑟_{𝑠𝑝,𝑠𝑝+𝑠𝑜+𝑠𝑖},…,𝑟_{𝑠𝑝+𝑠𝑜,𝑠𝑝+𝑠𝑜+𝑠𝑖}) to be realized on a PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), where 𝑟_𝑖,𝑘 is the number of the connection pairs (𝑝_𝑖,𝑗,𝑝_𝑘,𝑙) required to be connected through PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). For example, let AS = {(𝑝_1,1,𝑝_7,2), (𝑝_1,2,𝑝_3,1), (𝑝_3,2,𝑝_7,1)} to be routed on a PSN_𝐶(2,2,2,2,4) and a PSN_SU(2,2,2,2,4), which have been respectively shown in Figures 6 and 7. The RRV for the given AS on PSB(2,2,2,4) is 𝑟⃗ = (1_1,3, 0, 0, 0, 1_1,7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1_3,7, 0, 0, 0, 0, 0). We have already shown in Figures 10(a) or 10(b) that the RRV 𝑟⃗ = (1_1,3, 0, 0, 0, 1_1,7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1_3,7, 0, 0, 0, 0, 0) can be routed on a PSB_SU(2,2,2,4). Since any external terminal in 𝑃_𝑖 can be connected to a free internal terminal in 𝑇_𝑖 without blocking through a crossbar CB_𝑖(𝑛,𝑚), we show in Figures 11(a) and 11(b) two possible routing solutions for the given AS on a PSN_SU(2,2,2,2,4) switching network. Instances in Figures 12(a) and 12(b) show that the same AS is not routable on a PSN_𝐶(2,2,2,2,4) switching network, because the RRV 𝑟⃗ = (1_1,3, 0, 0, 0, 1_1,7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1_3,7, 0, 0, 0, 0, 0) contains at least one connection that cannot be routed on a PSB_𝐶(2,2,2,4) as already shown in Figures 9(b) and 9(c). Therefore, we conclude a PSN_𝐶(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) switch network constructed with a PSB_𝐶(𝑚,𝑠), where 𝑚=𝑛 is not rearrangeable. In the following, we prove that a PSN_𝐶(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) with 𝑚≤𝑛 is not rearrangeable.

(a)

(b)

Figure 11 

Instances of an AS routable on a PSNSU(2,2,2,2,4).

(a)

(b)

Figure 12 

Instances of the same AS not routable on a PSN𝐶(2,2,2,2,4).

Theorem 1. A 3-sided switching network 𝑃𝑆𝑁_𝐶(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is not rearrangeable for 𝑚≤𝑛, 𝑚∈𝑒𝑣𝑒𝑛, 𝑆=𝑠_𝑝+𝑠_𝑜+𝑠_𝑖, 𝑠_𝑝≥1, 𝑠_𝑜≥1, and 𝑠_𝑖≥1.

Proof. Observably, if a PSN_𝐶(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) with 𝑚=𝑛 is not rearrangeable, then a PSN_𝐶(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) with 𝑚<𝑛 is not rearrangeable. Thus, we need to prove that a PSN_𝐶(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is not rearrangeable.

Arbitrarily select three sides 𝑖, 𝑘, and 𝑢 of a PSN_𝐶(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), 1≤𝑖≤𝑠_𝑝<𝑘≤𝑠_𝑝+𝑠_𝑜<𝑢≤𝑆, we form an assignment AS={(𝑝_𝑖,1,𝑝_𝑢,1), (𝑝_𝑖,2,𝑝_𝑢,2), …, (𝑝_{𝑖,𝑛−1},𝑝_{𝑢,𝑛−1}), (𝑝_𝑖,𝑛,𝑝_𝑘,𝑛), (𝑝_𝑘,1,𝑝_𝑢,𝑛)} to be connected between the 𝑃_𝑖∈𝑃_𝑃, 𝑃_𝑘∈𝑃_𝑂, and 𝑃_𝑢∈𝑃_𝐼 on a PSN_𝐶(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). The RRV for routing AS_𝐷 on a PSB_𝐶(𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is 𝑟⃗=(0,…,0,𝑟_𝑖,𝑘=1,0,…,0,𝑟_𝑖,𝑢=𝑛−1,0,…,0,𝑟_𝑘,𝑢=1,0,…,0), as shown in Figure 4(a). Since a PSB_𝐶(𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is equivalent to 𝑛 isolated PSB_𝐶(1,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖)’s, the first 𝑟_𝑖,𝑢=(𝑛−1) can be realizable on (𝑛−1) isolated PSB_𝐶(1,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖)’s, as shown in Figure 4(b). But, we cannot find enough disjoint paths to simultaneously realize an 𝑟_𝑖,𝑘=1 and an 𝑟_𝑘,𝑢=1 on the last PSB_𝐶(1,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), as shown in Figure 4(b). Thus, this AS cannot be realizable on a PSN_𝐶(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), because this RRV 𝑟⃗ contains at least one connection that cannot be routed on a PSB_𝐶(𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). Therefore, the PSN_𝐶(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is not rearrangeable.

In the following, we will explore the properties of the semiuniversal and polygonal switch block PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) and show a PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) switching network constructed with semiuniversal PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), where 𝑚≥𝑛 is rearrangeable.

2.2. Semiuniversal and Polygonal Switch Blocks

Chang et al. and Shyu et al. [9–11] proposed a universal polygonal switch block PSB_𝑈(𝑚,𝑆) to improve the routability in a Field Programmable Gate Array routing network. Fan et al. [12] designed and proved a class of optimum PSB(𝑚,𝑆) for all even 𝑚 and 𝑆≥2. A PSB_𝑈(𝑚,𝑆) is an 𝑆-sided switch block with 𝑚 terminals on each side of the block; and a terminal from one side of PSB_𝑈(𝑚,𝑆) can be interconnected to another terminal in the remaining sides. A polygonal switch block PSB(𝑚,𝑆) is said to be universal [9–11] if any RRV 𝑟⃗=(𝑟_1,2, 𝑟_1,3, …, 𝑟_1,𝑆, 𝑟_2,3, …,𝑟_2,𝑆,…,𝑟_2,𝑆,…,𝑟_{𝑆−1,𝑆}) satisfying the following set of inequalities can be realizable on a PSB(𝑚,𝑆), for 𝑚∈even: 𝑟_1,1+𝑟_1,2+⋯+𝑟_1,𝑆𝑟≤𝑚,_2,1+𝑟_2,2+⋯+𝑟_2,𝑆⋮𝑟≤𝑚,_𝑆,1+𝑟_𝑆,2+⋯+𝑟_𝑆,𝑆≤𝑚, (1) where 0≤𝑟_𝑖,𝑘≤𝑚 for 1≤𝑖,𝑘≤𝑆, and 𝑟_𝑖,𝑘=𝑟_𝑘,𝑖,for1≤𝑖≠𝑘≤𝑆,0,for1≤𝑖=𝑘≤𝑆. (2)

Note that the number of connections interconnecting through each side of PSB(𝑚,𝑆) cannot exceed 𝑚; this dimensional constraint [9–11] is characterized by the preceding 𝑆 inequalities, one for each side.

Label the terminals on the 𝑖th side of a PSB(𝑚,𝑆) as 𝑇_𝑖={𝑡_𝑖,1,𝑡_𝑖,2,…,𝑡_𝑖,𝑚} for 1≤𝑖≤𝑆. A generic universal switch block has been proposed by Shyu et al. [11]. As shown in Algorithm 3, the algorithm can be used to construct an 𝑆-side universal switch block PSB_𝑈(𝑚,𝑆) with 𝑚 terminals on each side. That is to say, any RRV 𝑟⃗ satisfying the dimension constraint (i.e., the number of connections on each side of a PSB(𝑚,𝑆) is at most 𝑚) is realizable on a PSB_𝑈(𝑚,𝑆), for 𝑆≥2 and 𝑚∈even [12]. For example, Figure 13(b) shows a universal PSB_𝑈(2,6).

Algorithm: Universal switch block PSB𝑈(𝑚,𝑆,𝒯,SW). Input: 𝑆=𝑠𝑝+𝑠𝑜+𝑠𝑖—number of sides of the polygonal switch block; 𝑚—number of terminals on each side of the polygonal switch block, 𝑚∈even. Output: (𝒯,SW); 𝒯: set of terminals; SW: set of switches. (1)   𝒯←𝑡𝑖,𝑗,∀𝑖=1,2,…,𝑆,∀𝑗=1,2,…,𝑚; (2)  SW←∅; (3)   for  𝑖=1  to  𝑆−1  do (4)     for  𝑘=𝑖+1  to  𝑆  do (5)       for  𝑗=1  to  𝑚  do (6)        SW←SW∪𝑡𝑖,𝑗,𝑡𝑘,𝑚−𝑗+1; (7)  Return  (𝒯,SW)

Algorithm 3 

Algorithm for constructing an 𝑆-sided universal switch block of size 𝑚.

Figure 13 

Semiuniversal and universal polygonal switch block. (a) A semiuniversal PSBSU(2,2,2,4) and (b) its equivalent to a universal PSB𝑈(2,8) minus some switches in (c).

Since a semiuniversal PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) in a PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) does not allow any two internal terminals in the same set of 𝑇_𝑃, 𝑇_𝑂, and 𝑇_𝐼 to be interconnected, where 𝑇_𝑃=𝑇₁∪𝑇₂∪⋯∪𝑇_𝑠𝑝, 𝑇_𝑂=𝑇_𝑠𝑝+1∪𝑇_𝑠𝑝+2∪⋯∪𝑇_{𝑠𝑝+𝑠𝑜}, and 𝑇_𝐼=𝑇_{𝑠𝑝+𝑠𝑜+1}∪𝑇_{𝑠𝑝+𝑠𝑜+2}∪⋯∪𝑇_{𝑠𝑝+𝑠𝑜+𝑠𝑖}, we have to modify Algorithm 3 to construct our PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). Algorithm 2 removes the switches SW(𝑡_𝑖,𝑗,𝑡_𝑘,𝑙), where 𝑡_𝑖,𝑗 and 𝑡_𝑘,𝑙 belong to the same set of 𝑇_𝑃, 𝑇_𝑂, and 𝑇_𝐼 from PSB_𝑈(𝑚,𝑆), 𝑆=𝑠_𝑝+𝑠_𝑜+𝑠_𝑖. For example, Figure 13(a) shows a semiuniversal switch block PSB_SU(2,2,2,4), which is equal to a universal PSB_𝑈(2,8) in Figure 13(b) minus some prohibited switches in Figure 13(c). That is to say, a semiuniversal switch block PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) contains a partial topology of the universal switch block PSB_𝑈(𝑚,𝑆).

In the following, we redefine the properties of the semiuniversal and polygonal switch block PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). A polygonal switch block PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is said to be Semiuniversal (SU) if any RRV 𝑟⃗=(𝑟_1,𝑠𝑝+1,𝑟_1,𝑠𝑝+2,…,𝑟_1,𝑆,𝑟_2,𝑠𝑝+1,…,𝑟_2,𝑆,…,𝑟_{𝑠𝑝,𝑠𝑝+𝑠𝑜+1},…,𝑟_{𝑠𝑝,𝑆},  …,𝑟_{𝑠𝑝+𝑠𝑜,𝑆}) satisfying the following set of inequalities is realizable on a PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖): 𝑟_1,𝑠𝑝+1+𝑟_1,𝑠𝑝+2+⋯+𝑟_1,𝑆𝑟≤𝑚,_2,𝑠𝑝+1+𝑟_2,𝑠𝑝+2+⋯+𝑟_2,𝑆⋮𝑟≤𝑚,_𝑆,1+𝑟_𝑆,2+⋯+𝑟_{𝑆,𝑠𝑝+𝑠𝑜}≤𝑚, (3) where 0≤𝑟_𝑖,𝑘=𝑟_𝑘,𝑖≤𝑚, 𝑚∈even, 𝑆=𝑠_𝑝+𝑠_𝑜+𝑠_𝑖 for 1≤𝑖,𝑘≤𝑆, and 𝑇_𝑖 and 𝑇_𝑘 belong to two different sets of 𝑇_𝑃, 𝑇_𝑂, and 𝑇_𝐼.

Note that the number of connections interconnecting through each side of PSB(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) cannot exceed 𝑚; this dimensional constraint is characterized by the preceding 𝑆 inequalities, one for each side. Thus, the PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) constructed by Algorithm 2 is semiuniversal. Also, any RRV 𝑟⃗ satisfying the dimension constraint is simultaneously realizable on a PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖).

3. Rearrangeable 3-Sided Switching Networks

Since the programmable switches usually have high resistance and capacitance and occupy a large area, a rearrangeable 3-sided switching network PSN has routability and area efficiency. A 3-sided switching network PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) can be constructed with 𝑆CB(𝑛,𝑚) crossbars and a semiuniversal PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). Based on the semiuniversality of a PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) and the properties of a crossbar CB(𝑛,𝑚), we proceed to prove that the constructed PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is rearrangeable.

Theorem 2. A 3-sided switching network 𝑃𝑆𝑁_SU(𝑛, 𝑚, 𝑠_𝑝, 𝑠_𝑜, 𝑠_𝑖) is rearrangeable if and only if 𝑚≥𝑛, 𝑚∈𝑒𝑣𝑒𝑛, 𝑆=𝑠_𝑝+𝑠_𝑜+𝑠_𝑖, 𝑠_𝑝≥1, 𝑠_𝑜≥1, and 𝑠_𝑖≥1.

Proof. Observably, if a PSN_SU(𝑛, 𝑚, 𝑠_𝑝, 𝑠_𝑜, 𝑠_𝑖) with 𝑚=𝑛 is rearrangeable, then a PSN_SU(𝑛, 𝑚, 𝑠_𝑝, 𝑠_𝑜, 𝑠_𝑖) with 𝑚≥𝑛 is rearrangeable. Thus, we need to prove that a PSN_SU(𝑛, 𝑛, 𝑠_𝑝, 𝑠_𝑜, 𝑠_𝑖) is rearrangeable, 𝑛∈even.
A PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is used to connect the external terminals of 𝑃_𝑃, 𝑃_𝑂, and 𝑃_𝐼 to each other. Let 𝑃_𝑃=𝑃₁∪𝑃₂∪⋯∪𝑃_𝑠𝑝 (𝐼/𝑂 terminals), 𝑃_𝑂=𝑃_𝑠𝑝+1∪𝑃_𝑠𝑝+2∪⋯∪𝑃_{𝑠𝑝+𝑠𝑜} (output terminals), and 𝑃_𝐼=𝑃_{𝑠𝑝+𝑠𝑜+1}∪𝑃_{𝑠𝑝+𝑠𝑜+2}∪⋯∪𝑃_{𝑠𝑝+𝑠𝑜+𝑠𝑖} (input terminals), where 𝑃_𝑖={𝑝_𝑖,1,𝑝_𝑖,2,…,𝑝_𝑖,𝑛} on a CB_𝑖(𝑛,𝑛), 1≤𝑖≤𝑆. The connection pair (𝑝_𝑖,𝑗,𝑝_𝑘,𝑙) is a point-to-point connection, where 𝑝_𝑖,𝑗 and 𝑝_𝑘,𝑙 belong to different sets of 𝑃_𝑃, 𝑃_𝑂, and 𝑃_𝐼. An assignment AS={(𝑝_𝑖,𝑗,𝑝_𝑘,𝑙)} represents a set of connection pairs to be connected; thus each external terminal appears in at most one pair. The PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is rearrangeable if any assignment AS is realizable.
(If) Any assignment AS={(𝑝_𝑖,𝑗,𝑝_𝑘,𝑙)} can be connected on PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), since each connection pair (𝑝_𝑖,𝑗,𝑝_𝑘,𝑙)∈AS is required to be connected by passing CB_𝑖---PSB---CB_𝑘, we can obtain that this kind of RRV 𝑟⃗=(𝑟_1,𝑠𝑝+1, 𝑟_1,𝑠𝑝+2, …, 𝑟_{1,𝑠𝑝+𝑠𝑜+𝑠𝑖}, 𝑟_2,𝑠𝑝+1, …, 𝑟_{2,𝑠𝑝+𝑠𝑜+𝑠𝑖}, …, 𝑟_{𝑠𝑝,𝑠𝑝+1}, …, 𝑟_{𝑠𝑝,𝑠𝑝+𝑠𝑜+𝑠𝑖}, …, 𝑟_{𝑠𝑝+𝑠𝑜,𝑠𝑝+𝑠𝑜+𝑠𝑖}) for any given AS to be realized on a PSN_SU(𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), where 𝑟_𝑖,𝑘 represents the number of type-(𝑖,𝑘) connections between 𝑃_𝑖 and 𝑃_𝑘. Furthermore, this RRV 𝑟⃗ satisfying the dimension constraint is realizable on a semiuniversal PSB_SU(𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), due to the number of connection pairs in AS interconnecting through each side of PSB_SU(𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) does not exceed 𝑛. Therefore, for each (𝑝_𝑖,𝑗,𝑝_𝑘,𝑙)∈AS, we can find a connection path (𝑡_𝑖,𝑞,𝑡_{𝑘,𝑛−𝑞+1}) between 𝑇_𝑖 and 𝑇_𝑘 after the RRV 𝑟⃗ has been realized on a PSB_SU(𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), where 1≤𝑞≤𝑛. Then the connection (𝑝_𝑖,𝑗,𝑝_𝑘,𝑙) is realizable by programmed three switches, one switch SW(𝑡_𝑖,𝑞,𝑡_{𝑘,𝑛−𝑞+1}) in the PSB_SU(𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) and two other switches SW(𝑝_𝑖,𝑗,𝑡_𝑖,𝑞) and SW(𝑝_𝑘,𝑙,𝑡_{𝑘,𝑛−𝑞+1}) in the CB_𝑖(𝑛,𝑛) and CB_𝑘(𝑛,𝑛), respectively. Therefore, any given assignment AS for a PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is realizable, because there exist in the PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) disjoint paths connecting all the pairs of terminals given in the assignment AS. Thus, a PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) switching networks with 𝑚≥𝑛 is rearrangeable.
(Only if) If in a PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) with 𝑚<𝑛, we have an assignment AS={(𝑝_𝑖,1,𝑝_𝑘,1), (𝑝_𝑖,2,𝑝_𝑘,2), …, (𝑝_𝑖,𝑛,𝑝_𝑘,𝑛)} to be connected between the 𝑃_𝑖 and 𝑃_𝑘 on a PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), where 𝑃_𝑖 and 𝑃_𝑘 belong to different sets of 𝑃_𝑃, 𝑃_𝑂, and 𝑃_𝐼, since each connection pair (𝑝_𝑖,𝑗,𝑝_𝑘,𝑙)∈AS is connected by passing blocks CB_𝑖---PSB---CB_𝑘. In each CB_𝑖(𝑛,𝑚), we cannot find enough disjoint paths to connect all the 𝑛 external terminals in 𝑃_𝑖 to all the 𝑚 internal terminals in 𝑇_𝑖, which in turn are connected to the 𝑖th side of a PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖), due to 𝑚<𝑛. Thus, this AS is not realizable on a PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) with 𝑚<𝑛.

4. Minimize the Number of Switches

We have shown a rearrangeable 3-sided switching network PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) in the above section. Now, we start to explore the effect of the parameters 𝑠_𝑝,𝑠_𝑜,𝑠_𝑖, and 𝑛 in a PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) on the switch-efficiency, and we try to find proper 𝑠_𝑝,𝑠_𝑜,𝑠_𝑖, and 𝑛 values to minimize the number of switches needed in a rearrangeable PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) to interconnect terminal pairs from the three sets of 𝑃_𝑃, 𝑃_𝑂, and 𝑃_𝐼. We assume that the set of 𝑃_𝑃, 𝑃_𝑂, and 𝑃_𝐼 have 𝑁_𝑃=𝑠_𝑝×𝑛, 𝑁_𝑂=𝑠_𝑜×𝑛, and 𝑁_𝐼=𝑠_𝑖×𝑛 external terminals, respectively.

Since the number of switches in 𝑆CB(𝑛,𝑛) crossbars is equal to 𝑆𝑛²=(𝑠_𝑝+𝑠_𝑜+𝑠_𝑖)𝑛² and the number of switches in a polygonal switch block PSB_SU(𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is equal to 𝑛(𝑠_𝑝𝑠_𝑜+𝑠_𝑝𝑠_𝑖+𝑠_𝑜𝑠_𝑖), we denote the number of switches in a PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) as SW_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). By summing the number of switches in all the above blocks, we have SW_SU𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖=𝑠_𝑝+𝑠_𝑜+𝑠_𝑖𝑛²+𝑛𝑠_𝑝𝑠_𝑜+𝑠_𝑝𝑠_𝑖+𝑠_𝑜𝑠_𝑖. (4) Substituting 𝑠_𝑝=𝑁_𝑃/𝑛, 𝑠_𝑜=𝑁_𝑂/𝑛, and 𝑠_𝑖=𝑁_𝐼/𝑛 into (4) results in SW_SU𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖=𝑛𝑁_𝑃+𝑁_𝑂+𝑁_𝐼+𝑁_𝑃𝑁_𝑂+𝑁_𝑃𝑁_𝐼+𝑁_𝑂𝑁_𝐼𝑛. (5) Let 𝑑SW/𝑑𝑛=0 and solve for 𝑛, since 𝑁_𝑃, 𝑁_𝑂, and 𝑁_𝐼 are constant, we have 𝑑SW_SU𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖=𝑁𝑑𝑛^𝑃+𝑁_𝑂+𝑁_𝐼−𝑁_𝑃𝑁_𝐼+𝑁_𝑃𝑁_𝑂+𝑁_𝑂𝑁_𝐼𝑛²=0, (6) which implies 𝑛=𝑁_𝑃𝑁_𝐼+𝑁_𝑃𝑁_𝑂+𝑁_𝑂𝑁_𝐼𝑁_𝑃+𝑁_𝑂+𝑁_𝐼,𝑠_𝑝=𝑁_𝑃𝑛,𝑠_𝑜=𝑁_𝑂𝑛,𝑠_𝑖=𝑁_𝐼𝑛,𝑑²SW𝑑𝑛²>0. (7)

This indicates that the function SW_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) has minimum value at 𝑛=(𝑁_𝑃𝑁_𝐼+𝑁_𝑃𝑁_𝑂+𝑁_𝑂𝑁_𝐼)/(𝑁_𝑃+𝑁_𝑂+𝑁_𝐼), SW_SU𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖=2𝑁_𝑃+𝑁_𝑂+𝑁_𝐼𝑁_𝑃𝑁_𝐼+𝑁_𝑃𝑁_𝑂+𝑁_𝑂𝑁_𝐼. (8)

From (8), we have that a PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) with 𝑛=(𝑁_𝑃𝑁_𝐼+𝑁_𝑃𝑁_𝑂+𝑁_𝑂𝑁_𝐼)/(𝑁_𝑃+𝑁_𝑂+𝑁_𝐼) contains the number of switches to a minimum. Given a PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) interconnecting terminals pairs from 𝑃_𝑃, 𝑃_𝑂, and 𝑃_𝐼, where the set of 𝑃_𝑃, 𝑃_𝑂, and 𝑃_𝐼 have 𝑁_𝑃, 𝑁_𝑂, and 𝑁_𝐼 external terminals, respectively. Tables 2 and 3 show the number of switches needed in rearrangeable PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) each of which varies with 𝑛. In Table 2, the rearrangeable switching network PSN_SU(8,8,8,4,16) with 𝑛=8 (from (8)) is the best choice for interconnecting terminals pairs from the three terminal sets in terms of the number of switches. Furthermore, in Table 3, the rearrangeable switching network PSN_SU(12,12,12,8,16) with 𝑛=11.7 (from (8)) is the best choice for interconnecting terminals pairs from the three terminal sets.

Table 2 

Number of switches needed in five rearrangeable PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜, 𝑠_𝑖)s for interconnecting terminal pair from three terminal sets, where 𝑁_𝑃=64, 𝑁_𝑂=32, and 𝑁_𝐼=128 terminals.

Table 3 

Number of switches needed in five rearrangeable PSN_SU(𝑛,𝑛,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖)s for interconnecting terminal pair from three terminal sets, where 𝑁_𝑃=144, 𝑁_𝑂=96, and 𝑁_𝐼=192 terminals.

5. Polygonal FPGA

Figure 2 shows a model of polygonal FPGA (PFPGA), which consists of many clusters of logic block and 𝐼/𝑂 pins interconnected by a three-sided polygonal switching network. In this study, we investigate the logic block based on a cluster of 4-input look-up tables (LUTs). The three-sided polygonal switching network consists of 𝑆 connection blocks (CBs) and an 𝑆-sided polygonal switch block (PSB). Each connection block is connected to one of the 𝑆 sides of the polygonal switch block. All the above blocks contain many programmable switches. The polygonal switching network is a three-stage three-sided switching network [4] for connecting inputs of logic-block, outputs of logic-block, and 𝐼/𝑂 pins to interconnect each other. First, the input and output pins of cluster-based logic blocks and 𝐼/𝑂 pins are connected to the related connection blocks (CBs), which are then interconnected by a three-sided polygonal switch block (PSB). That is, the first and third stages consist of 𝑆 CBs and the second stage is a PSB with 𝑆 sides. In this PFPGA, any two terminals of the three groups in a PFPGA can be connected with fewer than three switches. Thus, the speed performance of a PFPGA can be improved.

Figure 14 shows that the basic logic block (BLB) [18] of our PFPGA has 𝑟=5 inputs and 1 output excluding the “global clock”. A BLB consists of a 4-input LUT and a register, and the BLB output can be either the registered or unregistered version of the LUT output. A BLB contains configurable digital circuits that can be used to implement different logic functions. As shown in Figure 15, the complete cluster-based logic block (CLB) is comprised of 𝑘 BLB, denoted as CLB(𝑘). A CLB(𝑘) has 𝑟𝑘 inputs and 𝑘 outputs. Let 𝑛=𝑟𝑘 on a CB(𝑛,𝑚); then 𝑟𝑘 inputs of a CLB(𝑘) are connected to one CB(𝑛,𝑚) of CB_𝐼, and 𝑟𝑘 outputs of 𝑟CLB(𝑘)’s connected to one CB(𝑛,𝑚) of CB_𝑂. Let 𝐿 be the total number of BLB’s in a PFPGA with 𝐵𝐼/𝑂 pins, as shown in Figure 2. We can obtain the following three parameters 𝑠_𝑖, 𝑠_𝑜, and 𝑠_𝑝 for a PFPGA: 𝑠_𝑖=𝐿𝑘,𝑠_𝑜=𝐿𝑛,𝑠_𝑝=𝐵𝑛,𝑆=𝑠_𝑖+𝑠_𝑜+𝑠_𝑝,𝑛=𝑟𝑘. (9)

Figure 14 

Basic logic block.

Figure 15 

Cluster-based logic block.

The key factors to the PFPGA switch-efficiency and speed-efficiency are the structure of its switching network PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) structure and the granularity of its cluster-based logic blocks CLB(𝑘). That is to say, the parameters 𝑘 and 𝑚 in a PFPGA affect its speed performance, die size, and routability.

Cluster-based logic blocks have two other advantages over single BLB logic blocks. First, in an FPGA composed of logic clusters, many nets will be completely contained within a logic cluster. If these nets are routed using multiplexers within a cluster, the delay of these multiplexers is less than that of the main FPGA. Secondly, clustering 𝑘 BLB’s into one logic cluster will greatly reduce the placement time by a factor of 𝑘, which is of increasing concern in today’s large FPGA’s.

5.1. Number of Switches in a PSN_SU

Let 𝐿 be the total number of BLB’s in a PFPGA with 𝐵𝐼/𝑂 pins, and a BLB has 𝑟 inputs and 1 output. The complete cluster-based logic block (CLB) is composed of 𝑘 BLB’s, denoted as CLB(𝑘). The number of switches in polygonal switching network PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is obtained as follows.

Because we have the following facts:(i)the number of switches in 𝑆CB(𝑛,𝑚)’s is equal to 𝑆×𝑚×𝑛,(ii)the number of switches in a PSN_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is equal to 𝑚(𝑠_𝑝𝑠_𝑜+𝑠_𝑝𝑠_𝑖+𝑠_𝑜𝑠_𝑖), where 𝑛=𝑟𝑘, 𝑠_𝑖=⌈𝐿/𝑘⌉, 𝑠_𝑜=⌈𝐿/𝑛⌉, 𝑠_𝑝=⌈𝐵/𝑛⌉, and 𝑆=𝑠_𝑖+𝑠_𝑜+𝑠_𝑝, and 𝐿, 𝐵 and 𝑟 are constants.

Denote the number of switches in a PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) as SW_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖). By summing the number of switches in all the above blocks, we have SW_SU𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖=𝑆𝑚𝑛+𝑚𝑠_𝑝𝑠_𝑜+𝑠_𝑝𝑠_𝑖+𝑠_𝑜𝑠_𝑖. (10)

From (10), SW_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) is determined by the 𝑘 and 𝑚 values. In the following section, we will find proper 𝑘 values and 𝑚 to minimize the number of switches needed in a polygonal switching network through experiments.

5.2. Experimental Results

To explore the effects of 𝑘 and 𝑚 values of a polygonal switching network on the switch-efficiency in a PFPGA with 𝐿 BLB’s and 𝐵𝐼/𝑂 pins, we have implemented a maze router [19–21] in C language and executed the codes on an IBM System M3. We examine the effect of two parameters, 𝑘 and 𝑚, on the switch performance using the CGE [1] and SEGA [22] benchmark circuits.

By routing different cluster size of logic blocks, the switch performance of a three-sided polygonal switching network was evaluated. From the results of a CLB(5), as listed in Table 4, we first determine the minimum number of tracks 𝑚 required to complete the 100% routing of each circuit, using three-sided polygonal switching networks PSN_SU(𝑛, 𝑚, 𝑠_𝑝, 𝑠_𝑜, 𝑠_𝑖). Then we can find the SW_SU(𝑛, 𝑚, 𝑠_𝑝, 𝑠_𝑜, 𝑠_𝑖) value by substituting the values of 𝑛, 𝑚, 𝑠_𝑖, 𝑠_𝑜, and 𝑠_𝑝 into (10).

Table 4 

Minimum number of tracks and switches needed for detailed-routing completion for CLB(5).

Figure 16 shows that the numbers of programmable switches SW_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) used in the 14 benchmarks vary with CLB(𝑘), where 𝑘=1,2,…,12. Experimental results demonstrate that the switches number used in PSN_SU is minimum for a PFPGA with CLB(5) (for CGE) and CLB(3) (for SEGA), respectively. We assume that the available pin count of a PFPGA is 𝐵=84 and the number of BLB is about 208. Therefore, our PFPGA consists of 52 CLB(5) and 𝐵=84𝐼/𝑂 pins interconnected by a three-sided polygonal switching network SW_SU(𝑛=20, 𝑚=25, 𝑠_𝑖=52, 𝑠_𝑜=11, 𝑠_𝑝=5).

Figure 16 

Minimum number of switches needed for 14 benchmark circuits.

5.3. VLSI Chip Implementation of the PFPGA

The chip layout of our PFPGA using a 0.18 μm CMOS technology is shown in Figure 17. The polygonal switching network area of a PFPGA is 1255 μm × 1350 μm. And the total area of this PFPGA is 1550 μm × 1600 μm. So we can calculate the ratio of routing area to total area to be 68.81%. Since routing area typically takes 70–90 percent of the total chip area in general FPGA [3]. So we conclude that the polygonal FPGA gets more area utilization.

Figure 17 

Chip layout of the PFPGA.

In our proposed PFPGA architecture, we provide a three-stage routing resources concept. The first and third stages of routing are the connection blocks in two CLBs, which can meet local signal routing requirements. And the second layer of routing is the polygonal switch block, which is used to connect any output signal of a CLB to any input signal of a CLB. Thus, the longest distance in our PFPGA is only three stages. The maximum point-to-point of PSN_SU delay is 13 ns. So we conclude that the architecture of PFPGA has better speed improvement. As mentioned above, this chip architecture uses less number of programmable switches and the speed performance of a PFPGA can be achieved. Thus, it is very suitable for VLSI implementation.

6. Conclusions

This paper first proposed a generic three-stage and rearrangeable three-sided switching network PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) used in the PFPGA for all even 𝑚. The PSN consists of 𝑆CB(𝑛,𝑚) crossbars interconnected by a semiuniversal polygonal switch block PSN_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) with 𝑆 sides. We not only provide the designers with a rearrangeable PSN_SU(𝑛,𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) with 𝑚≥𝑛 for connecting terminal pairs from three disjoint terminal sets to each other but also determinate the important parameter 𝑛 to minimize the number of switches needed in that network. We also propose a PFPGA that consists of many logic blocks interconnected by a PSN_SU. We investigate the effect of the PSN_SU structure and the granularity of its interconnecting cluster-based logic blocks on the switch-efficiency and speed-efficiency performance. Experimental results demonstrate that the switch-efficiency and speed-efficiency are improved so it holds promise as a practical PFPGA with polygonal switching network.

Acknowledgment

This work was partly supported by the National Science Council, Taiwan, under Grant NSC 101-2221-E-019-071.