Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

Table 2

Qualitative comparison of logic designs [2].

Logic designs	No. of MOS logic networks	Output driving capability	Input/output decoupling	Signal rails	Robustness
CMOS	n + p	Medium-good	Yes	Single	High
CPL	2n	Good	Yes	Dual	Medium
DPL	2n + 2p	Good	Yes	Dual	High