Design a Bioamplifier with High CMRR

Abstract

A CMOS amplifier with differential input and output was designed for very high common-mode rejection ratio (CMRR) and low offset. This design was implemented by the 0.35 μm CMOS technology provided by TSMC. With three stages of amplification and by balanced self-bias, a voltage gain of 80 dB with a CMRR of 130 dB was achieved. The related input offset was as low as 0.6 μV. In addition, the bias circuits were designed to be less sensitive to the power supply. It was expected that the whole amplifier was then more independent of process variations. This fact was confirmed in this study by simulation. With the simulation results, it is promising to exhibit an amplifier with high performances for biomedical applications.

1. Introduction

For biomedical applications, a voltage amplifier with a gain of 80 dB and a high CMRR is required as a building block in front-end subsystems [1, 2]. Since the voltage level of physiologic signals at the front-end subsystem is very weak, processes for analog signals usually include several steps of amplification, filtering, offset adjustment, and electrical conditioning. After suitable processing, the signal will then be large enough and effectively suitable for analog-to-digital conversion at later stages [3–5].

In considering the physiological signals extracted from human bodies, the amplitude of an electrocardiographic (ECG) signal is usually less than 100 μV. Such value is very weak as compared to the noise floor and imperfection of the commonly used operational amplifiers (OPAs). An instrumentation amplifier (IA) is usually employed to achieve the required performances.

In addition to the requirement of high voltage gain in constructing the amplifiers for an IA, another important requirement for the amplifiers is CMRR. According to the recommendations of Association of the Advancement of Medical Instrumentation (AAMI), CMRR is required to be higher than 90 dB with the open-loop voltage gain higher than 80 dB.

In this study, the 0.35 μm CMOS technology of TSMC was employed in designing a high performance amplifier.

In our study, a high-voltage-gain amplifier was tried with a self-biasing technique to have a high CMRR and low input offset and to be less sensitive to process variations. The simulation was performed based on the models supported by Chip Implementation Center (CIC). The related results will be illustrated.

2. Design Details

2.1. Design of the Differential Amplifier

For the purposes of high CMRR and low offset at the input, differential configuration with a symmetrical floor planning in layout will be preferred in the design of an amplifier.

Figure 1 shows the schematic of an amplifier with the differential configuration both at the input and at the output. In this circuit, transistors 𝑀₁ and 𝑀₂ are the differential pair for amplification. The block with 𝐼_𝑇 and 𝑅_𝑇 forms a tail current bias. The resistors 𝑅_𝐷1, 𝑅_𝐷2, 𝑅_𝐿1, and 𝑅_𝐿2 are taken as the loads.

Figure 1 

Schematic of the differential amplifier.

Figure 2 shows an alternative representation of the amplifier in Figure 1. The input and output signals can be decomposed into the common and the differential modes. With this decomposition, the performance of the amplifier in the common mode and the differential mode can be discussed separately.

Figure 2 

Representation of the amplifier in the common and the differential modes.

In the common mode, the two output voltages will be the same if the circuit is ideal in a form of total symmetry. This requires that the branches for 𝐼_𝐷1 and 𝐼_𝐷2 are matched with 𝑅_𝐿1=𝑅_𝐿2 and 𝑅_𝐷1=𝑅_𝐷2.

For the current bias as the tail, a current mirror with a stable reference current, 𝐼_REF, can be employed in the integrated circuits to give a high output resistance, 𝑅_𝑇.

Other techniques to improve the performance of this amplifier will be discussed in detail in the following.

For practical design, there exist variations in the devices even with the integrated circuit technology. The output voltage will not be zero for the common input condition. For example, the imperfections in the threshold voltage and the transconductance of the MOS transistors and the variation in 𝑅_𝐷 are uncorrelated. The resulted input offset voltage can be expressed as 𝑉_OS≡𝑉_{OUT𝑉𝑑=0}𝐴_𝑑=𝑉_OV2Δ𝑅_𝐷𝑅_𝐷²+Δ(𝑊/𝐿)(𝑊/𝐿)²+Δ𝑉_TH𝑉_OV/2². (1) According to the analysis in the common mode and the differential mode, the output voltage can be expressed as the sum of the amplification of the signals of both modes. The relations for the outputs can be written at follows:𝑉_𝑂1=𝐴_𝑑2×𝑣_𝑑+𝐴_cm×𝑣_cm,𝑉_𝑂2𝐴=−^𝑑2×𝑣_𝑑+𝐴_cm×𝑣_cm, (2a)(2b)where 𝑣_𝑑≡𝑣_in1−𝑣_in2, 𝑣_cm≡(𝑣_in1+𝑣_in2)/2, 𝐴_𝑑 is the differential-mode voltage gain, and 𝐴_cm is the common-mode gain. It is similar for the expression for 𝑉_𝑂2. The common-mode rejection ratio (CMRR) is then defined as 𝐴CMRR≡^𝑑𝐴_cm. (3) A good amplifier is required to have a high 𝐴_𝑑 with a nearly zero 𝐴_cm. Due to the variations in the fabrication process, it is a big challenge to achieve a high CMRR with a low input offset. In this study, a balanced bias technique was employed to reduce the sensitivity to the process variation. Good properties of this amplifier have been confirmed in the postlayout simulation.

2.2. Tristage Amplifier

In this design, three stages of amplification were employed to achieve the required voltage gain and CMRR at the same time for weak biosignals. Figure 3 shows the detailed circuit in this design. Table 1 gives the specifications for this design.

Table 1 

Specifications for the bioamplifier.

Figure 3 

Structure of the tristage amplifier.

As seen in Figure 3, the first stage is composed of 𝑀₁--𝑀₅. The second stage includes 𝑀₆--𝑀₁₂. These two stages can be used as an operational transconductance amplifier (OTA) [6, 7] or a folded cascade amplifier [8]. The third stage comprising 𝑀₁₃ and 𝑀₁₄ forms a type 𝐴 common-source (CS) amplifier to drive loads.

Transistors 𝑀_𝑆1--𝑀_𝑆6 provide a bias current for the first-stage amplifier. The source of biasing for the second-stage amplifier comes from the balanced self-bias current mirror, 𝑀₈--𝑀₁₁, in Figure 3. In this part, the biasing currents were less sensitive to the level of the power supply. In addition, the complementary arrangement of the loads at the first-stage and the second-stage amplifiers would reduce the variation of the amplification if there are changes in the NMOS and PMOS. The bias voltage for the third stage comes from 𝑀₉ in the second stage. Since the bias currents in 𝑀₉ and 𝑀₁₁ were constant, the gate bias for 𝑀₁₃ would be constant. Therefore, the properties of the whole amplifier would be less affected by the uncertainties in fabrication.

For the design strategy, the first stage was designed to achieve a high CMRR rather than a high voltage gain. The overall voltage gain was boosted at the second and the third stages. Since this amplifier was designed for biomedical applications, the voltage gain was tried to be as high as possible with a moderate small bandwidth around 100 Hz. At the third stage, a clamping circuit can keep dynamic tracking of the output gain such that the voltage gain would be less affected by variations in the transistors.

In addition to the electrical considerations, the layout and circuit for the first and second stages were designed as symmetrical as possible. In this way, the common signals would be cancelled out in the differential structure. Therefore, the equivalent input offset would be suppressed effectively.

With the above techniques, an amplifier with high voltage gain, high CMRR, low offset, and low drift voltage can be achieved and confirmed in the simulation.

For our circuit, the level of the power supply was set at 3.3 V by setting 𝑉_DD at 1.65 V and −𝑉_SS at −1.65 V. In the meanwhile, the power dissipation was specified below 1 mW for portable operations. With this constraint, as explained by (4), the total current consumed in this circuit cannot be more than 0.303 mA: 𝐼_Supply≤𝑃_𝐷,Spec.𝑉_Supply=0.303mA. (4) As for the stability consideration, the phase margin (PM) of this amplifier was tuned to be 60° in our simulation [9]. In this design, we select 𝐺_𝑚3≥10𝐺_𝑚2. And the second pole was set as 𝜔_𝑃2≥2.2×𝜔_𝑇. Therefore, the Miller compensation capacitor, 𝐶_𝐶, was selected to be 18 pF by the following calculation: 𝐶_𝐶𝐺≥2.2×^𝑚1𝐺_𝑚2×𝐶_𝑂2=0.22𝐶_𝑂2. (5)

2.3. Transistor Dimensions

In general, the tail current was required to be higher than the product of the screw rate and 𝐶_𝐶. In this study, this product was 10 μA for the second stage. Since the screw rate for the case of light loads is not required strictly, the tail current at stage 2 was selected as 15 μA.

The bias currents for the two branches through 𝑀₆ and 𝑀₇ equally divide the tail current into 𝐼_𝐷6=𝐼_𝐷8=𝐼_𝐷10=𝐼_𝐷7=𝐼_𝐷9=𝐼_𝐷11=7.5 μA.

With this bias current, the transconductance, 𝑔_𝑚, and the gate-to-source voltage, 𝑉_GS, can be designed by a suitable dimension ratio, 𝑊/𝐿, by the following relations: 𝐼_𝐷=12⋅𝜇_𝑛⋅𝐶_𝑜𝑥⋅𝑊𝐿⋅𝑉_OV²⋅1+𝜆𝑉_DS,𝑔_𝑚=𝜇_𝑛⋅𝐶_𝑜𝑥⋅𝑊𝐿⋅𝑉_OV⋅1+𝜆𝑉_DS=2𝜇_𝑛⋅𝐶_𝑜𝑥⋅𝑊𝐿⋅𝐼_𝐷⋅1+𝜆𝑉_DS=2×𝐼_𝐷𝑉_OV, (6)(7) where the overdrive voltage 𝑉_OV≡𝑉_GS−𝑉_th.

For the third stage, its transconductance gain, 𝐺_𝑚3, is the same as 𝑔_𝑚13 of 𝑀₁₃. We chose 𝐺_𝑚3≥10𝐺_𝑚2; that is, 𝐺_𝑚3≥590 μA/V and 𝑔_𝑚13=𝐺_𝑚3=600 μA/V. In addition, the overdrive voltage for 𝑀₁₃ was selected as 𝑉_OV13=0.2 V; that is, 𝑉_GS13≡𝑉_OV13+𝑉_tn=0.85 V. Therefore, 𝑉_DS13=𝑉_DS14=1.65 V. The dimension ratio for (𝑊/𝐿)₁₃ can be determined by (6).

In this design, we used 𝑀_𝑆1∼𝑀_𝑆6 and a resistor 𝑅_𝑆 to form a self-bias circuit with a boot-strapping positive feedback. The current controlled by 𝐼_REF can be expressed as 𝐼_REF×𝑅_𝑆=𝑉_GS𝑆6−𝑉_GS𝑆5=𝐼_REF𝐾_𝑆6−𝐼_REF𝐾_𝑆5. (8) By (8), we selected the dimension ratio of 𝑀_𝑆5 to be 1/4 of that of 𝑀_𝑆6, that is, 𝑊𝐿_𝑆5=14𝑊𝐿_𝑆6. (9) The resistance can be obtained as follows: 𝑅_𝑆=1𝐼_REF𝐼_REF𝐾_𝑆5. (10) The reference current was set as 𝐼_REF=5 μA. The dimension ratio for 𝑀_𝑆1∼𝑀_𝑆4 can also be derived by (6).

3. Simulation and Verification before Fabrication

In this study, HSPICE with the device models for 0.35 μm CMOS technology from TSMC was employed for the simulation and analysis. The performance of the whole circuit was verified first in the prelayout simulation. Then, the physical layout was implemented and the related parameters were extracted. With the obtained information of the physical layout, the postlayout simulation was performed to check the feasibility of our layout. Corner simulations were also performed to check the effect of the process variation on the performance of our amplifier.

Figures 4–7 illustrate the related performances with 5 corner conditions in fabrication. Table 2 lists other performance items with the 5 corners. With these results, we can find that the voltage gain in Figure 6 can be kept higher than 80 dB. And the variation of the obtained gains due to the uncertainty in fabrication can be smaller than 5 dB. It can also be found in Figures 4 and 5 that the phase margin is much larger than 60°. In Figure 5, we can confirm that the variation of phases is insignificant. As shown in Figure 7, the obtained CMRR is as high as 130 dB for frequency up to 10 kHz. The variation of CMRR due to the fabrication is also insignificant. With these results, a bio-amplifier both with a very high CMRR and a high voltage gain at the same time can be expected for the fabricated chips.

Table 2 

Variations of the simulated properties of the bio-amplifier with 5 fabrication corners.

Figure 4 

Frequency response for the bio-amplifier in the typical fabrication condition (TT).

Figure 5 

Simulated phases for the bio-amplifier in 5 corner conditions.

Figure 6 

Simulated gains for the bio-amplifier in 5 corner conditions.

Figure 7 

Simulated CMRRs for the bio-amplifier in 5 corner conditions.

4. Conclusion

A bio-amplifier with high gain and high CMRR was designed and verified in this study. According to the obtained performance properties in Table 2, it is promising that a process independent performance can be obtained for this amplifier.

Acknowledgments

The authors acknowledge the support from Chip Implementation Center (CIC) and Chang Bin Show Chwan Memorial Hospital with the research resources. Partial financial support from National Science Council (NSC), republic of china, is also acknowledged.