FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

<table>Screen shot of the measured delay for the 64-bit TMR-RCA using a Tektronix TLA 7012 logic analyzer. The delay obtained at a particular transition is highlighted by the red arrows.</table>

VLSI Design

fig17

Figure 17

Figure 17: FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders 