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VLSI Design
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2013
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Article
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Tab 1
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Research Article
Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor
Table 1
Hazard-1. Type-1: RAW.
Dependent register
Instruction
EX.Register
AND, OR, NOT, XOR, ADD, SUB, MUL, MOV
ID.Register.Source
AND, OR, NOT, XOR, ADD, SUB, MUL, MOV