Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

Table 3

The design specifications’ comparisons.

Type	Properity
	Gate count	Frequency	Max net delay
Single	48656	26.449 MHz	14.952 ns
16-cycle	68926 (+41.7%)	19.173 MHz (−27.5%)	18.674 ns (+24.9%)
8-cycle (Method-2)	47058 (+3.2%)	29.951 MHz (+1.3%)	15.607 ns (+4.3%)